• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.8 no.6
• /
• pp.2139-2151
• /
• 2014

Embedded system testing, especially long-term reliability testing, of flash memory solutions such as embedded multi-media card, secure digital card and solid-state drive involves strategic decision making related to test sample size to achieve high test coverage. The test sample size is the number of flash memory devices used in a test. Earlier, there were physical limitations on the testing period and the number of test devices that could be used. Hence, decisions regarding the sample size depended on the experience of human testers owing to the absence of well-defined standards. Moreover, a lack of understanding of the importance of the sample size resulted in field defects due to unexpected user scenarios. In worst cases, users finally detected these defects after several years. In this paper, we propose that a large number of potential field defects can be detected if an adequately large test sample size is used to target weak features during long-term reliability testing of flash memory solutions. In general, a larger test sample size yields better results. However, owing to the limited availability of physical resources, there is a limit on the test sample size that can be used. In this paper, we address this problem by proposing a self-adaptive reliability testing scheme to decide the sample size for effective long-term reliability testing.

• Journal of the Korea Society of Computer and Information
• /
• v.24 no.3
• /
• pp.1-9
• /
• 2019

This paper presents three potential risks in an environment that simultaneously performs the garbage collection and wear leveling in NAND flash memory. These risks may not only disturb the lifespan improvement of NAND flash memory, but also impose an additional overhead of page migrations. In this paper, we analyze the interference of garbage collection and wear leveling and we also provide two theoretical considerations for lifespan prolongation of NAND flash memory. To prove two solutions of three risks, we construct a simulation, based on DiskSim 4.0 and confirm realistic impacts of three risks in NAND flash memory. In experimental results, we found negative impacts of three risks and confirmed the necessity for a coordinator module between garbage collection and wear leveling for reducing the overhead and prolonging the lifespan of NAND flash memory.

• Journal of the Semiconductor & Display Technology
• /
• v.9 no.2
• /
• pp.67-72
• /
• 2010

Recently increasing application of flash memory in mobile and ubiquitous related devices is due to its non-volatility, fast response time, shock resistance and low power consumption. Following this trend, SSD(Solid State Disk) using multiple flash chips, instead of hard-drive based storage system, started to widely used for its advantageous features. However, flash memory based storage subsystem should resolve the performance bottleneck for writing in perspective of speed and lifetime according to its disadvantageous physical property. In order to provide tangible performance, solutions are studied in aspect of reclaiming of invalid regions by decreasing the number of erasures and distributing the erasures uniformly over the whole memory space as much as possible. In this paper, we study flash memory recycling algorithms with multiple management units and demonstrate that the proposed algorithm provides feasible performance. The proposed method utilizes the partitions of the memory space by utilizing threshold values and reconfigures the management units if necessary. The performance of the proposed policies is evaluated through a number of simulation based experiments.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.38 no.1
• /
• pp.26-45
• /
• 2001

The Flash memory market: is an exciting market that has quickly over the last 10 years. Recently Flash memory provides a high-density. truly non-volatile, high performance read write memory solutions, also is characterized by low power consumption, extreme ruggedness and high reliability. Flash memory is an optimum solution for large nonvolitilc storage operations such as solid file storage, digital video recorder, digital still camera, The MP3 player and other portable multimedia communication applications requiring non-volatility. Regardless of the type of Flash memory, Flash media management software is always required to manage the larger Flash memory block partitions. This is true, since Flash memory cannot be erased on the byte level common to memory, but must be erased on a block granularity. The management of a Flash memory manager requires a keen understanding of a Flash technology and data management methods. Though Flash memory's write performance is relatively slow, the suggested algorithm offers a higher maximum write performance. Algorithms so far developed is not suitable for applications which is requiring more fast and frequent accesses. But, the proposed algorithm is focused on the justifiable operation even in the circumstance of fast and frequent accesses.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.147-155
• /
• 2017

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.4
• /
• pp.291-302
• /
• 2013

NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.

• Journal of the Korea institute for structural maintenance and inspection
• /
• v.18 no.2
• /
• pp.30-37
• /
• 2014

In this study, we studied how to perform the structural analysis which need a large-capacity flash memory with the computer program when the flash memory storage of a personal computer has no enough room for the analysis of structure. As one of the solutions of this problem, the blocking method of stiffness matrix, which is a method that stiffness matrix is divided by a few blocks and each block is sequentially used for the calculation of matrix decomposition, is proposed and an algorithm available in computer program is derived on the method. Finally, A structural analysis program (sNs) based on this study is developed and the correctness and efficiency of the algorithm is founded through some examples which are fundamental in structural analysis.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.22 no.1
• /
• pp.57-65
• /
• 2012

People leave voicemails or record phone conversations in their daily cell phone use. Sometimes important voice data is deleted by the user accidently, or purposely to cover up criminal activity. In these cases, deleted voice data must be able to be recovered for forensics, since the voice data can be used as evidence in a criminal case. Because cell phones store data that is easily fragmented in flash memory, voice data recovery is very difficult. However, if there are identifiable patterns for the deleted voice data, we can recover a significant amount of it by researching images of it. There are several types of voice data, such as QCP, AMR, MP4, etc.. This study researches the data recovery solutions for EVRC codec and AMR codec in QCP file, Qualcumm's voice data format in cell phone.