• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.41-45
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• 2015

From 20nm technology node, the finFET has become standard device for ULSI's. However, the finFET process made stacking gate non-volatile memory obsolete. Some reported capacitor-less DRAM structure by utilizing the FBE. We present possible non-volatile memory device structure similar to the dual gate MOSFET. One of the gates is left floating. Since body of the finFET is only 40nm thick, control gate bias can make electron tunneling through the floating gate oxide which sits across the body. For programming, gate is biased to accumulation mode with few volts. Simulation results show that the programming electron current flows at the interface between floating gate oxide and the body. It also shows that the magnitude of the programming current can be easily controlled by the drain voltage. Injected electrons at the floating gate act similar to the body bias which changes the threshold voltage of the device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.101-101
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• 2007

We fabricated floating gate non-volatile memory devices with Si nanocrystals embedded in $SiN_x$ layer to achieve higher trap density. The average size of Si nanocrystals embedded in $SiN_x$ layer was ranging from 3 nm to 5 nm. The MOS capacitor and MOSFET devices with Si nanocrystals embedded in $SiN_x$ layer were analyzed the charging effects as a function of Si nanocrystals size.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.67-68
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• 2006

Floating gate non-volatile memory devices with Au nano-particles embedded in SiON or $SiO_2$ dielectrics were fabricated by digital sputtering method. The size and the density of Au are 4nm and $2{\times}10^{-12}cm^{-2}$, respectively. The floating gate memory of MOSFET with 5nm tunnel oxide and 45nm control oxide have been fabricated. This devices revealed a memory effect which due to proGrainming and erasing works perform by a gate bias stress repeatedly.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.647-648
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• 2006

This paper presents the design results of peripheral circuits of non-volatile memory of nano floating gate cells. The designed peripheral circuits included command decoder, decoders, sense amplifiers and oscillator, which are targeted with 0.35um technology EEPROM process for operating test and reliable test. The simulation results show each operation and test mode of output voltage for word line, bit line, well and operating of sense amplifier.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1123-1127
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• 2009

This paper expands the scope of application of the thin film transistor (TFT) in which it is used as the switching element by making the amorphous silicon TFT with the non-volatile memory device,. It is the thing about the amorphous silicon non-volatile memory device which is suitable to an enlargement and in which this uses the additionally cheap substrate according to the amorphous silicon use. As to, the amorphous silicon TFT non-volatile memory device is comprised of the glass substrates and the gate, which evaporates on the glass substrates and in which it patterns the first insulation layer, in which it charges the gate the floating gate which evaporates on the first insulation layer and in which it patterns and the second insulation layer in which it charges the floating gate, and the active layer, in which it evaporates the amorphous silicon on the second insulation layer the source / drain layer which evaporates the n+ amorphous silicon on the active layer and in which it patterns and the source / drain layer electrode in which it evaporates on the source / drain layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1044-1046
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• 2009

Here we report the architecture for a non-volatile n-type memory paper field-effect transistor. The device is built using the hybrid integration of natural cellulose fibers (pine and eucalyptus fibers embedded in an ionic resin), which act simultaneously as substrate and gate dielectric, with amorphous GIZO and IZO oxides as gate and channel layers, respectively. This is complemented by the use of continuous patterned metal layers as source/drain electrodes.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.20.1-20.1
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• 2011

The nano-sized quantum structure has been an attractive candidate for investigations of the fundamental physical properties and potential applications of next-generation electronic devices. Metal nano-particles form deep quantum wells between control and tunnel oxides due to a difference in work functions. The charge storage capacity of nanoparticles has led to their use in the development of nano-floating gate memory (NFGM) devices. When compared with conventional floating gate memory devices, NFGM devices offer a number of advantages that have attracted a great deal of attention: a greater inherent scalability, better endurance, a faster write/erase speed, and more processes that are compatible with conventional silicon processes. To improve the performance of NFGM, metal nanocrystals such as Au, Ag, Ni Pt, and W have been proposed due to superior density, a strong coupling with the conduction channel, a wide range of work function selectivity, and a small energy perturbation. In the present study, bismuth metal nanocrystals were self-assembled within high-k $Bi_2Mg_{2/3}Nb_{4/3}O_7$ (BMN) films grown at room temperature in Ar ambient via radio-frequency magnetron sputtering. The work function of the bismuth metal nanocrystals (4.34 eV) was important for nanocrystal-based nonvolatile memory (NVM) applications. If transparent NFGM devices can be integrated with transparent solar cells, non-volatile memory fields will open a new platform for flexible electron devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.269-275
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• 2003

Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.08a
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• pp.144-145
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• 2008