• Journal of Multimedia Information System
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• v.6 no.1
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• pp.7-14
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• 2019

This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.1
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• pp.20-26
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• 2021

Recent systems contain hardware and software components together for faster execution speed and less power consumption. In conventional hardware and software co-design, the ratio of software and hardware was divided by the designer's empirical knowledge. To find optimal results, designers iteratively reconfigure accelerators and applications and simulate it. Simulating iteratively while making design change is time-consuming. In this paper, we propose a hardware and software co-design platform for energy-efficient FPGA accelerator design. The proposed platform makes it easy for designers to find an appropriate hardware ratio by automatically generating application program code and hardware code by parameterizing the components of the accelerator. The co-design platform based on the Vitis unified software platform runs on a server with Xilinx Alveo U200 FPGA card. As a result of optimizing the multiplication accelerator for two matrices with 1000 rows, execution time was reduced by 90.7% and power consumption was reduced by 56.3%.

• International Journal of Aeronautical and Space Sciences
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• v.9 no.2
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• pp.121-128
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• 2008

Modularized GPS software defined radio (SDR) has many advantages of applying and modifying algorithm. Hardware based GPS receiver uses many hardware parts (such as RF front, correlators, CPU and other peripherals) that process tracked signal and navigation data to calculate user position, while SDR uses software modules, which run on general purpose CPU platform or embedded DSP. SDR does not have to change hardware part and is not limited by hardware capability when new processing algorithm is applied. The weakness of SDR is that software correlation takes lots of processing time. However, in these days the evolution of processing power of MPU and DSP leads the competitiveness of SDR against the hardware GPS receiver. This paper shows a study of modulization of GPS software platform and it presents development of the GNSS software platform using MATLAB Simulink™. We focus on post processing SDR platform which is usually adapted in research area. The main functions of SDR are GPS signal acquisition, signal tracking, decoding navigation data and calculating stand alone user position from stored data that was down converted and sampled intermediate frequency (IF) data. Each module of SDR platform is categorized by function for applicability for applying for other frequency and GPS signal easily. The developed software platform is tested using stored data which is down-converted and sampled IF data file. The test results present that the software platform calculates user position properly.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.172-174
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• 2007

In this paper, we designed a embedded system that will perform a primary role of Tangible Space implementation. This hardware includes function of image capture through camera interface, image process and sending off image information by LAN(local area network) or WLAN(wireless local area network). We define this hardware as a network based Visual Agent Platform for Tangible Space, This Visual Agent Platform includes the software that is RTLinux and CORBA

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.1
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• pp.19-24
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• 2008

To reduce time-to-market, more and more embedded system developers and system-on-chip designers rely on microprocessor-based design methodology. ARM processor has been a major player in this industry over the last 10 years. However, there are many restrictions on developing embedded software using ARM processor in the early design stage. For those who are not familiar with embedded software development environment or who cannot afford to have an expensive embedded hardware equipment, testing their software on a real ARM hardware platform is a challenging job. To overcome such a problem, we have designed VMA (Virtual ARM Machine), which offers easier testing and debugging environment to ARM based embedded system developers. Major benefits that can be achieved by utilizing a virtual ARM platform are (1) reducing development cost, (2) lowering the entrance barrier for embedded system novices, and (3) making it easier to test and debug embedded software designs. Unlike many other purely software-oriented ARM simulators which are independent of real hardware platforms, VMA is specifically targeted on SYS-Lab 5000 ARM hardware platform, (designed by Libertron, Inc.), which means that VMA imitates behaviors of embedded software as if the software is running on the target embedded hardware as closely as possible. This paper will describe how VMA is designed and how VMA can be used to reduce design time and cost.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5B
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• pp.449-454
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• 2009

In this paper, we analyze the hardware and software platform for constructing the USN in the vessel environment. Specifically, we analyze the mote technology based on the CC2420 in the hardware platform and analyze the TinyOS platform in the software platform. We also analyze the physical layer of IEEE802.15.4 which is the standard of the USN communication. In the simulation, we evaluate the performance in the physical layer of ZigBee/IEEE 802.15.4 by using the MATLAB and verify the validity of constructing the USN in the vessel environment based on the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.127-138
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• 2012

In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1723-1728
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• 2010

In this paper we concentrate design and develop method about Multi-Channel Internet Radio Platform to broadcast music contents in large outlet and between spaces to protect music contents which have drastically widespread demage. we provide application concept and design rule of hardware path for Multi-Channel Connection and Multi Stream.

• International Journal of Contents
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• v.7 no.1
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• pp.23-28
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• 2011

In a SoC (system-on-chip) design, a design complexity is a big bottleneck. In order to overcome the design complexity, platform based design method is widely adopted for designers. Most complex SoCs need a heterogeneous design development environment for hardware and software co-design. In this paper, we discuss about some kinds of verification approaches with platform based design methodology at various abstraction levels of SoC design. We separate the verification process to two steps according to the different levels of verification. We employ a flexible SoC design environment to support simultaneous hardware and software development. We demonstrate the verification strategy of a target SoC design, IEEE 802.11a WLAN SoC.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.781-782
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• 2006

This treatise proposed environment for Embedded system's development. Virtual platform can help to solve problem that hardware designer can experience at design process of hardware. Compose circuit of most suitable that is verified before mix parts by various kinds method and compose circuit by board level because can do simulation with software and software that is optimized to hardware and offer flexibility that can test. Therefore, can shorten expense that is cost in development and time. Embody development platform for 8051 systems for verification of development platform, and compose and verified system in various kinds structure.