• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.21-29
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• 2004

Hot carrier degradation characteristics of Nano-scale CMOSFETs with dual gate oxide have been analyzed in depth. It is shown that, PMOSFET lifetime dominate the device lifetime than NMOSFET In Nano-scale CMOSFETs, that is, PMOSFET lifetime under CHC (Channel Hot Carrier) stress is much lower than NMOSFET lifetime under DAHC (Dram Avalanche Hot Carrier) stress. (In case of thin MOSFET, CHC stress showed severe degradation than DAHC for PMOSFET and DAHC than CHC for NMOSFET as well known.) Therefore, the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor in upcoming Nano-scale CMOSFET technology. In case of PMOSFETs, CHC shows enhanced degradation than DAHC regardless of thin and thick PMOSFETs. However, what is important is that hot hole injection rather than hot electron injection play a important role in PMOSFET degradation i.e. threshold voltage increases and saturation drain current decreases due to the hot carrier stresses for both thin and thick PMOSFET. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method. Therefore, suppression of PMOSFET hot carrier degradation or hot hole injection is highly necessary to enhance overall device lifetime or circuit lifetime in Nano-scale CMOSFET technology

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.60-66
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• 1998

The hot carrier induced performance degradation of 0.8${\mu}{\textrm}{m}$ RF NMOSFET has been investigated within the general framework of the degradation mechanism. The device degradation model of an unit finger gate MOSFET could be applied for the device degradation of the multi finger gate RF NMOSFET. The reduction of cut-off frequency and maximum frequency can be explained by the transconductance reduction and the drain output conductance increase, which are due to the interface state generation after the hot carrier stressing. From the correlation between hot carrier induced DC and RF performance degradation, we can predict the RF performance degradation just by the DC performance degradation measurement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.9-14
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• 2005

This paper reports the hot carrier induced RF performance degradation of bulk dynamic threshold voltage MOSFET (B-DTMOS) compared with bulk MOSFET (B-MOS). In the normal and moderate mode operations, the degradations of cut-off frequency $(f_{T})$ and minimum noise figure $(F_{min})$ of B-DTMOS are less significant than those of B-MOS devices. Our experimental results show that the RF performance degradation is more significant than the U performance degradation after hot carrier stressing. Also, the degradation characteristics of RF power Performance of B-DTMOS due to hot carrier effects are measured for the first time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.9
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• pp.638-643
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• 2003

Channel width dependence of hot-carrier effect in nMOSFET with shallow trench isolation is analyzed. $I_{sub}$- $V_{G}$ and $\Delta$ $I_{ㅇ}$ measurement data show that MOSFETs with narrow channel-width are more susceptible to the hot-carrier degradation than MOSFETs with wide channel-width. By analysing $I_{sub}$/ $I_{D}$, linear $I_{D}$- $V_{G}$ characteristics, thicker oxide-thickness at the STI edge is identified as the reason for the channel-width dependent hot-carrier degradation. Using the charge-pumping method, $N_{it}$ generation due to the drain avalanche hot-carrier (DAHC) and channel hot-electron (CHE) stress are compared. are compared.

• 전자공학회논문지 IE
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• v.45 no.4
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• pp.7-10
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• 2008

In this work investigates hot carrier stress on the RF power of SOI MOSFET using load-pull measurement. We found that the RF power characteristics are affected by the hot carrier stress, and the DC performance of SOI MOSFET is clearly degraded after hot carrier stress at constant voltage measurement. And these experimental observations can be explained by the change of DC performance degradation coefficient under hot carrier stress.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.433-436
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• 1998

Hot carrier induceed the performance degradation of sense amplifier circuit in DRAM has been measured and analyzed using 0.8.mu.m CMOS process. Simulation and experimental results show that the degradation of the MOS devices affects the decrease of the half-Vcc, voltage gain and the increase of the sensing voltage gain and the increase of the sensing voltage. The dominant degradation mechanism is the capacitance imblance in the bit-line pair. We carried out the spice simulation to investigate the degradation of the sense amplifier circuit.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.327-330
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• 2004

It is shown that the hot carrier degradation due to enhanced hot holes trapping dominates PMOSFETs lifetime both in thin and thick devices. Moreover, it is found that in 0.13 ${\mu}m$ CMOSFET the PMOS lifetime under CHC (Channel Hot Carrier) stress is lower than the NMOSFET lifetime under DAHC (Drain Avalanche Hot Carrier) stress. Therefore. the interface trap generation due to enhanced hot hole injection will become a dominant degradation factor. In case of thick MOSFET, the degradation by hot carrier is confirmed using charge pumping current method and highly necessary to enhance overall device lifetime or circuit lifetime in upcoming nano-scale CMOS technology.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.867-870
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• 1998

In this paper we simulated 0.30um NMOS transitor to analysis hot carrier degradation depend on As, As+P, P LDD structure. As a result we obtained As+P LDD structure was good hot carrier immunity. Also we find that hog carrier life time improved a sincresing P dose due to P dose helps in grading the nLDD junction. However As-only junction was poor due to junction high peak position located near the surface.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.5-8
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• 2002

Hot carrier induced device degradation is observed in thin-film, gate-all-around SOI transistor under DC stress conductions. We observed the more significant device degradation in GAA device than general single gate SOI device due to the degradation of edge transistor. Therefore, it is expected that the maximum available supply voltage of GAA transistor is lower than that o( bulk MOSFET or single gale SOI device.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.363-366
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• 1998

25.deg. C 에서 120.deg. C까지 온도를 증가시키면서 hot carrier effect에 의한 nMOSFET의 degradation을 drain current와 transconductance의 변화를 통해 알아보았다. 온도가 증가할수록 hot carrier에 의한 degradation 이 전체적으로 줄어드는 것을 볼수 있었다. stress를 가한 후 reverse mode로 측정하였는데 saturation 영역보다 linear 영역에서 drain current의 degradation이 크게 나탔으며 온도가 증가할수록 이러한 경향이 유지되면서 degradation이 감소하였다. transconductance는 linear 영역과 saturation 영역에서 각각 측정하였는데 온도가 증가할수록 linear 영역의 degradation이 더많이 감소하였다.