• Current Optics and Photonics
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• v.6 no.3
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• pp.270-281
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• 2022

Based on the transfer-matrix method (TMM), we report the characteristics of the interface states in one-dimensional (1D) composite structures consisting of two photonic crystals (PCs) composed of binary dielectrics A and B, with unit-cell configurations ABA (PC I) and BAB (PC II). The dependence of the interface states on the number of unit cells N and the boundary factor x are displayed. It is verified that the interface states are independent of N when the PC has inversion symmetry (x = 0.5). Besides, the composite structures support the formation of interface states independent of the PC symmetry, except that the positions of the interface states will be varied within the photonic band gaps. Moreover, the robustness of the interface states against nonuniformities is investigated by adding Gaussian noise to the layer thickness. In the case of inversion symmetry (x = 0.5) the most robust interface states are achieved, while for the other cases (x ≠ 0.5) interface states decay linearly with position inside the band gap. This work could shed light on the development of robust photonic devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.807-813
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• 1986

Measurements of interface states in a MOS capacitor by DLTS system using wideband monophase lock-in amplifier are discussed. A new signal analysis method that takes into account the bias pulse width and the gate off width is presented to remove the errors in the measured parameters of interface states resulting from the traditional method which neglects the effect of those widths. Theoretical calculations are made for the parameters related to the rate window, signal to noise ratio, and the energy resolution. On the grounds of this discussion, interface states of the MOS capacitor on p-type substrate of (110) orentation are measured with the optimal gate-off width with respect to the S/N ratio and the energy resolution. The results are interface state density of the order of 10**10 (cm-\ulcornereV**-1) to 10**11 (cm-\ulcornereV**-1) in the energy range of Ev+0.15(dV) to Ev+0.5(eV), and constant capture cross section of the order of 10**-16 (cm\ulcorner.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• Journal of Magnetics
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• v.6 no.3
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• pp.80-82
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• 2001

We have investigated magnetism of $Fe_2 /Ir_4$(001) superlattice in terms of a first-principles calculation by using an all-electron full-potential linearized augmented plane-wave (FLAPW) method within the generalized gradient approximation (GGA). We considered two magnetic states, the ferromagnetic (FM) and antiferromagnetic (AFM) coupled states between the Fe layers. It was found that the FM state was energetically more stable than the AFM one by 0.166 eV. Calculated magnetic moments of the Fe layers were, in absolute values, 2.45$\mu_B$ and 2.30 $\mu_B$for the FM and AFM states, respectively. We also found that the Ir layers had very small magnetic moments less than 0.1 $\mu_B$ for both magnetic states. In all the magnetic states, the subinterface Ir layers were coupled antiferromagnetically to the interface Ir layers, while the interface Ir layers were always coupled frerromagnetically to the interface Fe layers. These results contradicted to recent experimental reports of magnetically "dead"Fe layers in Fe/Ir superlattices for which the Fe layer thickness was less than two atomic layers. We attributed that the experimentally observed "dead"Fe layers were due to possible interdiffusion between Ir and Fe layers.en Ir and Fe layers.

• Proceedings of the Korea Society of Design Studies Conference
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• 1995.11a
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• pp.40-41
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• 1995

• Electrical & Electronic Materials
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• v.16 no.9
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• pp.62.1-62
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• 2003

Silicon oxide with thickness lee than 9 nm is fabricated by tube furnace oxidation. Nitrogen is added to dilute the oxidation rate. Aluminum dots with radius of 0.05 cm are deposited on the oixde. High frequency capacitance-voltage(HF C-V), conductance-voltage(G-V) and current-voltage(I-V) characteristics are measured. Annealing under nitrogen atmosphere is carried out with different time and at different temperature. Densities of the interface states before and after annealing are compared. After annealing, a decrease in density of the interface states is found. Experiments show that 45$0^{\circ}C$ annealing for 30 minutes has the lowest density of the interface states.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.293-296
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• 2016

Using capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements, the electrical properties of Cu/n-InP Schottky diodes were investigated. The values of C and G/ω were found to decrease with increasing frequency. The presence of interface states might cause excess capacitance, leading to frequency dispersion. The negative capacitance was observed under a forward bias voltage, which may be due to contact injection, interface states or minority-carrier injection. The barrier heights from C-V measurements were found to depend on the frequency. In particular, the barrier height at 200 kHz was found to be 0.65 eV, which was similar to the flat band barrier height of 0.66 eV.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.53-63
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• 1993

Device degradations by the Fowler-Nordheim tunneling have been studide. The changes of device characteristics such as the threshold voltage, subthreshold slope, I-.or. curves have been measured after bidirectionally stressing n-channel MOSFET's and p-channel MOSFET's. Also the interface states have been directly measured by the charge pumping methodIt is shown that the change of interface states is determined by the number of hole carriers tunneling the gate oxide and electrons which are trapped in the gate oxide. Also, in this paper, we propose a model for device lifetime limited by the increase of interface states.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.9
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.