• Journal of the Korean Society for Precision Engineering
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• 제23권7호
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• pp.138-145
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• 2006

A nanopatterning technique was proposed and demonstrated for low cost and mass productive process using the scanning probe lithography (SPL) and soft lithography. The nanometer scale structure is fabricated by the localized generation of oxide patterning on the H-passivated (100) silicon wafer, and soft lithography was performed to replicate of nanometer scale structures. Both height and width of the silicon oxidation is linear with the applied voltagein SPL, but the growth of width is more sensitive than that of height. The structure below 100 nm was fabricated using HF treatment. To overcome the structure height limitation, aqueous KOH orientation-dependent etching was performed on the H-passivated (100) silicon wafer. Soft lithography is also performed for the master replication process. Elastomeric stamp is fabricated by the replica molding technique with ultrasonic vibration. We showed that the elastomeric stamp with the depth of 60 nm and the width of 428 nm was acquired using the original master by SPL process.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.633-636
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• 2005

Imprint lithography is a promising method for high-resolution and high-throughput lithography using low-cost equipment. As with other nanoimprint methods, ultraviolet-nanoimprint lithography (UV-NIL) resolution appears to be limited only by template resolution, and offers a significant cost of ownership reduction when compared to other next generation lithography (NGL) methods such as EUVL and 157 nm lithography. The purpose of this paper is to suggest optimum values of control parameters of Imprio 100 manufactured by Molecular Imprint, Inc., which is the first commercially available UV-NIL tool, for sound nanoimprint. UV-NIL experiments were performed on Imprio 100 to find dispensing recipe for avoiding air entrapment. Dispensing recipe related to residual layer thickness and uniformity was optimized and 40 nm thick residual layer was achieved.

• Journal of Sensor Science and Technology
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• 제28권4호
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• pp.251-255
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• 2019

We propose a two-step lithography process to minimize edge-bead issues caused by thick photoresist (PR) coating. In the conventional PR process, the edge bead can be efficiently removed by applying an edge-bead removal (EBR) process while rotating the silicon wafer at a high speed. However, applying conventional EBR to the production of desired PR mold with unique negative patterns cannot be used because a lower rpm of spin coating and a lower temperature in the soft bake process are required. To overcome this problem, a two-step lithography process was developed in this study and applied to the fabrication of a polydimethylsiloxane (PDMS) film having super-hydrophobic characteristics. Following UV exposure with a first photomask, the exposed part of the silicon wafer was selectively removed by applying a PR developer while rotating at a low rpm. Then, unique PR mold structures were prepared by employing an additional under-exposure process with a second mask, and the mold patterns were transferred to the PDMS. Results showed that the fabricated PDMS film based on the two-step lithography process reduced the height difference from 23% to 5%. In addition, the water contact angle was greatly improved by spraying of hydrophobic nanosilica on the dual-scaled PDMS surface.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2007년도 추계학술대회 논문집
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• pp.499-500
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• 2007

• Journal of Institute of Control, Robotics and Systems
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• 제14권4호
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• pp.332-335
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• 2008

PMMA light guiding plate with nano pattern was fabricated by nano imprint lithography method. A silicon mold for electroplating of nickel was fabricated by conventional photolithography process. A nickel stamp for nano imprint lithography was fabricated by electroplating process using silicon mold. The nano imprint lithography was performed on PMMA plate at $140^{\circ}C$ under pressure of 20kN. The nano pattern on PMMA plate was investigated using FE-SEM. It is shown that the patterns were well transferred for several steps and the nano imprint lithography method could be applied for fabricating patterns of light guiding plate.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Journal of the Korean Vacuum Society
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• 제5권4호
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• pp.309-314
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• 1996

We found that SOG which had been used in plarnarization of VLSI circuit fabrication at present could be used as a resist material for AFM lithography. In this experiment on the basis of previous studies, we improved the process flexibility by controlling the coating film thickness, etching time, etching selectively and proper applied voltage on the pattern size to apply for practical VLSI lithography process. We obtained pattern with the current of 5 nA at 60 V. The line width was 800 $\AA$. With the developed flexibility of SOG as a resist material, AFM lithography will be a expedient technique in the next generation DRAM fabrication.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.196-198
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• 2003

Classical lithography in semiconductor employs stepper technologies. Limits of this technology are clearly seen at structures below 100nm. Nano-imprinting lithography is a new method for generating patterns in submicron range at reasonable cost. In order to manufacture nano-imprinting lithography(NIL) equipment, several NIL manufacturers have been developing key technologies for realization of nano-imprinting process, recently. In this paper, we've been describe state-of-the-art and technology trends for nano-imprinting lithography equipments.

• Journal of the Korean Vacuum Society
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• 제19권2호
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• pp.96-104
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• 2010

We suggest here a cost-effective replica fabrication method for transparent and hard molds for imprinting lithography such as NIL and S-FIL. The process starts with the use of a replica hard mold from a master, using a polymer copy as a carrier. The polymer copy as a carrier was treated by soluble process for forming anti-adhesion layer. Duplicated hard molds can eliminate direct contact between a hard master and a patterned polymer on a substrate and the generated contamination of a master during the imprinting process. The replica hard mold exhibits the glass-like properties introduced here, such as transparency and hardness, make it appropriate for nanoimprint lithography and step-and-flash imprint lithography.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제33A권7호
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• pp.198-204
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• 1996

Electron beam lithography is one of the importnat technologies which can delineate deep submicron patterns. REcently, electron beam lithography is being applied in delineating the critical layers of semiconductor device fabrication. In this paper, we present a development simulation program for electron beam lithography and study the development profiles of resist when resist is exposed by the electron beam. Experimentally, the development parameter of positive and negative resists are measured and the data is applied to input parameter of the simulation program. Also simulation results are compared of the process results in the view of resist profiles. As a result, for PMMA and SAL 601 resist, the trend of simulation to the values of process parameters agree with real process results very well, so that the process results can be predicted by the simulation.