• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.907-910
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• 2003

We have developed Logic Design Training Kit for studying, actual training, designing of FPGA(Xillinx) or CPLD(ALTERA CPLD), the Digital Logic Device. This training kit has 12 matrix keys, RS232 port for serial communication and uses LED array. six FND(Dynamic), LCD as display part. That is standard specification for digital logic training kit. Special point of this kit is that we make two logic device trainig kit. This two logic device kit have more smaller and simple architecture because only uses one chip. That chip already includes a lot of functions that need for training kit, such as : complex logic circuit needed the two kind of logic devices, 16 way of system clock deviding function, serial communication interrupt....etc. We called that one chip is Center Bridge Chipset ; Xillinx FPGA Spartan2. User can select between using one device of FPGA or CPLD, or uses both them. Because of, Center Bridge Chipset has profitable architecture. it can work as Logic Device's networking with Master-Slave connection When using both logic devices.

• Journal of Practical Engineering Education
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• v.9 no.1
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• pp.41-48
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• 2017

In this paper, we proposed a method for digital logic circuit control, through arduino device programming with digital outputs, to design a curriculum for basic digital logic circuit practices. Curricula for arduino device programming and digital logic circuit are essentially practiced in engineering departments of colleges or high schools in South Korea. However, actual practice course lacks the experimental examples of digital logic circuit combined with arduino device programming. Furthermore, actual practice course lacks the curriculum in that students design and test their own digital logic circuits with the less cost than the oscilloscope. Therefore, to solve these problems in this paper, we proposed a curriculum for basic digital logic circuit practices during one semester. In this curriculum, students control and experiment their own digital logic circuits through arduino device programming with digital outputs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.12
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• pp.953-958
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• 2001

The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.314-321
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• 2020

Logic automated stimulus and response (LASAR) software is an automatic test program development tool for logic function test and fault detection of avionics components digital circuit cards. LASAR software needs to the information for the logic circuit function and input and output of the device. If there is no component information, normal component modeling is impossible. In this paper, component modeling is carried out through reverse design of programmable logic device (PLD) device without element information. The developed LASAR program identified failure detection rates through fault simulation results and single-seated fault insertion methods. Fault detection rates have risen by 3% to 91% for existing limited modeling and 94% for modeling through the reverse design. Also, the 22 case of stuck fault with the I/O pin of EP310 PLD were detected 100% to confirm the good performance.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.295-298
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• 2016

Future logic device over the FinFET generation requires a complete electrostatics and transport characteristic for low-power and high-speed operation as extremely scaled devices. Silicon, Germanium and III-V based nanowire-based MOSFET devices and few-layer TMDC (Transition metal dichalcogenide monolayers) based multi-gate devices have been brought attention from device engineers due to those excellent electrostatic and novel device characteristic. In this study, we simulated ultrascaled Si/Ge/InAs gate-all-around nanowire MOSFET and MoS2 TMDC based DG MOSFET and TFET device by tight-binding NEGF method. As a result, we can find promising candidates of the future logic device of each channel material and device structures.

• KIEAE Journal
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• v.14 no.3
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• pp.97-103
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• 2014

This study aimed at developing integrated logic for controlling heating device and openings of the double skin facade buildings. Two major logics were developed-rule-based control logic and artificial neural network based control logic. The rule based logic represented the widely applied conventional method while the artificial neural network based logic meant the optimal method. Applying the optimal method, the predictive and adaptive controls were feasible for supplying the advanced thermal indoor environment. Comparative performance tests were conducted using the numerical computer simulation tools such as MATLAB (Matrix Laboratory) and TRNSYS (Transient Systems Simulation). Analysis on the test results in the test module revealed that the artificial neural network-based control logics provided more comfortable and stable temperature conditions based on the optimal control of the heating device and opening conditions of the double skin facades. However, the amount of heat supply to the indoor space by the optimal method was increased for the better thermal conditioning. The number of on/off moments of the heating device, on the other hand, was significantly reduced. Therefore, the optimal logic is expected to beneficial to create more comfortable thermal environment and to potentially prevent system degradation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.70-81
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• 2002

This paper describes a new basic element which shows a synaptic operation for neural logic applications and shows function feasibility. A key device for the logic operation is the insulated-gate pn-junction device on SOI substrates. The basic element allows an interface quite compatible to that of conventional CMOS circuits and vMOS circuits.

• Journal of Biosystems Engineering
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• v.23 no.4
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• pp.365-372
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• 1998

This study was carried out to develop a nutrient-solution mixing-and-supplying system, which used a low-cost metering device instead of expensive metering pumps and a fuzzy logic controller. A low cost and precise overflow-type metering device was developed and evaluated by testing the flow discharge for the automatic nutrient-solution mixing-and-supplying system for snail-scale hydroponic sewers. The fuzzy logic controllers, which could predict and meet the desired values of EC and supply rate of nutrient solution were developed and verified by simulation and experiment. this fuzzy logic controller, whose algorithm consists of four crisp inputs, two crisp outputs and nine rules, was developed to predict the desired value of EC and supply rate of nutrient solution and two crisp inputs, one crisp output and nine rules used to control EC to the desired values. The nutrient-solution mixing-and-supplying system showed satisfactory EC control performance with the maximum overshooting of 0.035 mS/cm and the maximum settling time of 15 minutes in case of increasing 0.7 mS/cm. also, the accuracy of the overflow-type metering device in terms of the full-scale error was 2.29% when using solenoid valve only and 0.2% when using solenoid valve and flow control valve together.

• Proceedings of the Korean Nuclear Society Conference
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• 1996.11a
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• pp.191-196
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• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.

• Nuclear Engineering and Technology
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• v.44 no.6
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• pp.697-708
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• 2012

The majority of instrumentation and control (I&C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I&C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I&C systems. Therefore, existing NPPs are replacing the obsolete analog I&C systems with advanced digital systems. New NPPs are also adopting digital I&C systems because the economic efficiencies and usability of the systems are higher than the analog I&C systems. Digital I&C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.