• Journal of Institute of Control, Robotics and Systems
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• v.14 no.9
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• pp.939-947
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• 2008

The GPS tracking loop consists of three parts in general: discriminator, loop filter and DCO (Digitally Controlled Oscillator). The loop filter is the main part of the tracking loop designed to ensure a good tracking performance. Generally, the loop filter is designed using classical PI(Proportional Integral) control. Although the carrier Doppler and code Doppler are generated by the same relative movement between the satellite and the user, often, the loop filters for each tracking loop are designed separately and independently. Sometimes, they are used in a combined manner such as carrier aided code tracking, FLL assisted PLL, etc. For better GPS signal tracking, we need to design the FLL/PLL/DLL altogether optimally. The purpose of this paper is to design a GPS receiver tracking loop based on the Kalman filter in a combined manner. Also, the proposed GPS receiver tracking loop is compared with a conventional tracking loop in terms of the transfer function and the DCO input. This paper shows that conventional tracking loop is equal to the Kalman filter based tracking loop.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.8
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• pp.727-732
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• 2008

In this paper, the state-space representation of generalized complimentary filter is proposed. Complementary filter has the suitable structure to merge information from sensors whose frequency regions are complementary. First, the basic concept and structure of complementary filter is introduced. And then the structure of the generalized filter and its state-space representation are proposed. The state-space representation of complementary filter is able to design the complementary filter by applying modern filtering techniques like Kalman filter and $H_{\infty}$ filter. To show the usability of the proposed state-space representation, the design of Inertial Navigation System(INS) vertical channel damping loop using Global Positioning System(GPS) is described. The proposed GPS/INS damping loop lends the structure of Baro/INS(Barometer/INS) vertical channel damping loop that is an application of complementary filter. GPS altitude error has the non-stationary statistics although GPS offers navigation information which is insensitive to time and place. Therefore, $H_{\infty}$ filtering technique is selected for adding robustness to the loop. First, the state-space representation of GPS/INS damping loop is acquired. And next the weighted $H_{\infty}$ norm proposed in order to suitably consider characteristics of sensor errors is used for getting filter gains. Simulation results show that the proposed filter provides better performance than the conventional vertical channel loop design schemes even when error statistics are unknown.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.76-85
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• 1997

Charge-pump loop filter was designed using GaAs MESFET for GHz-range PLL system applications. Characteristics of charge-pump loop filter and stability of charge-pump PLL, system were analyzed. Performance specifications were defined and a charge-pump loop filter was designed that satisfies these specifications.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.907-910
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• 2000

QPSK 복조기는 위상 오차에 따른 문제점을 극복하기 위해 수신단에서는 반송파의 주파수와 위상을 tracking 하는 Carrier recovery loop부분이 필요하다〔1〕. Carrier recovery loop는 multiplier, arm filter, matched filter, decimator, loop filter, NCO로 구성이 된다〔2〕.기존 Carrier recovery loop의 NCO는 sine과 cosine의 lookup table을 갖는 구조로 되어있어, 전력소모가 크다는 문제점을 가지고 있다. 따라서 본 논문에서는 lookup table을 사용하지 않는 저 전력 구조의 QPSK복조기의 Carrier recovery loop의 NCO를 설계했다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.333-336
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• 2000

Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.