• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.83-86
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• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.457-462
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• 2014

This letter proposes a low-jitter DLL-based clock generator with two negative feedback loops. The main negative feedback loops suppress the jitter of DLL. The additional negative feedback loops suppress the delay-time variance of each delay stages. Both two negative feedback loops in a DLL results in suppressing the jitter of clock signal further. Measurement results of the DLL-based clock generator with two negative feedback loops fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process show 5.127-ps rms jitter and 47.6-ps peak-to-peak jitter at 1 GHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.33-39
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• 2013

There have been studies in improving jitter characteristic of delay locked loop (DLL) even it has a shorter jitter that of phase locked loop (PLL). These studies result in numerous architectures of DLL which improve jitter performance. The paper shows that the jitter characteristic can be improved with various loop filters in DLL. It has been designed with 1.8V $0.18{\mu}m$ CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.5
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• pp.353-363
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• 1990

This paper analyzes effect of Data Bit Jitter(DBJ) on the Bit Slip Rate(BSR) of the receiver Data Tracking Loop(DTL). In particular, we point out the characteristic jitter parameters that can be used to estimate the BSR performance for the low frequency parts respectively. We also propose a new format for the DBJ specification, which is more sophisticated than the conventional method but is believed to be more practical and accurate in predicting DBJ effect on the receiver BSR performance. In the proposed method, receive dependent parameters are identified and weighting between different parts of jitter spectrum are properly considered.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• Journal of the Optical Society of Korea
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• v.13 no.3
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• pp.373-378
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• 2009

An Ethernet passive optical network (EPON) is a low-cost, high-speed solution to the bottleneck problem of a broadband access network. This paper analyzes the delay and the jitter performance of dynamic bandwidth allocation (DBA) schemes for differentiated services in EPONs. Especially, the average packet delay and the delay jitter of the expedited forwarding (EF) traffic class are compared, with consideration as to whether a cyclic or an interleaved polling scheme is superior. This performance evaluation reveals that the cyclic polling based DBA scheme provides constant and predictable average packet delay and improved jitter performance for the EF traffic class without the influence of load variations.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1630-1633
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• 2002

In this paper, we proposed a new control system of the dividing ratio changeable type ADPLL (DCPLL). The DCPLL has been designed by us. However, in the DCPLL, there are some problems such as this curcuit is increased the output jitter on multiple frequency, and the output jitter is large on steady state. Then, the output jitter characteristic on multiple frequency is improved by using “rest-control” system. Also, output jitter decreases by using “W-edge (positive edge h negative edge)” system. We confirmed some characteristics of the DCPLL with the circuit simulator, PSpice.

• The Journal of the Acoustical Society of Korea
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• v.42 no.4
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• pp.298-303
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• 2023

This study aimed to investigate the clinical utility of voiced sentence tasks for voice evaluation. To this end, we analyzed the correlation between perturbation-based acoustic measurements [jitter percent (jitter), shimmer percent (shimmer), Noise to Harmonic Ratio (NHR)] using sustained vowel phonation, and cepstrum-based acoustic measurements [Cepstral Peak Prominence (CPP), Low/High spectral ratio (L/H ratio)] using voiced sentences. As a result of analyzing data collected from 65 patients with voice disorders, there was a significant correlation between the CPP and jitter (r = -.624, p = .000), shimmer (r = -.530, p = .000), NHR (r = -.469, p = .000).This suggests that the cepstrum measurement of voiced sentences can be used as an alternative to the analysis limitations of the pathological voice such as not possible perturbation-based acoustic measurement, and result difference according to the analysis section.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.276.2-278
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• 2000

In a recent years, a number of approaches have been studied, including passive, active, and hybrid mode-locking of semi-conductor lasers for short pulse generation and research has been devoted to achieve low timing-jitter operation since the timing jitter is unfavorable for system applications. Among the methods of mode locking, passive mode locking does not need external rf drives, and therefore the operation and fabrication procedures are simplified. In spite of these attractive advantages of passive mode-locked laser, it has critical drawbacks such as large timing jitter and the difficulty in synchronization with external circuits. Their inherent large timing jitter value was shown to be suppressed to certain levels by means of hybrid mode-locking technique$^{(1)}$ , where the saturable absorber section was modulated by an external signal with the cavity round trip frequency. Furthermore, the subharmonic mode-locking (SHML) technique alleviates the restrictions of high speed driving electronics. It has been demonstrated experimentally$^{(1)}$ that the hybrid subharmonic mode-locking technique has lead to significant reduction of the timing jitter. (omitted)