• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.216-226
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• 2015

The neutral beam injection generate ultra-high temperature energy in the tokamak of nuclear fusion. The neutral beam injection make up arc power supply, filament power supply and acceleration & deceleration power supply. The arc power supply has characteristics of low voltage and high current. Arc power supply generate arc through constant output of voltage and current. So this paper proposed suitable buck converter for low voltage and high current. The proposed buck converter used parallel switch because it can be increased capacity and decrease conduction loss. When an arc generated, the neutral beam injection chamber occur high voltage. And it will break output capacitor of buck converter. Therefore the output capacitor was removed in the proposed converter. Thus the proposed converter should be designed for the characteristics of low voltage and high current. Also, the arc power supply should be guaranteed for system stability. The proposed parallel buck converter enables the system stability of the divided low output voltage and high current. The proposed converter with constant output be the most important design of the output inductor. In this paper, designed arc power supply verified operation of system and stability through simulation and prototype. After it is applied to the 288[kW] arc power supply for neutral beam injection.

• Journal of Advanced Information Technology and Convergence
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• v.8 no.2
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• pp.59-67
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• 2018

The minimum power supply voltage of a typical bandgap current reference (BGCR) is limited by operating temperature and input common mode range (ICMR) of a feedback amplifier. A new BGCR using a bandgap voltage generator (BGVG) is proposed to minimize the effect of temperature, supply voltage, and process variation. The BGVG is designed with proportional to absolute temperature (PTAT) characteristic, and a feedback amplifier is designed with weak-inversion transistors for low voltage operation. It is verified with a $0.18-{\mu}m$ CMOS process with five corners for MOS transistors and three corners for BJTs. The proposed circuit is superior to other reported current references under temperature variation from $-40^{\circ}C$ to $120^{\circ}C$ and power supply variation from 1.2 V to 1.8 V. The total power consumption is $126{\mu}W$ under the conditions that the power supply voltage is 1.2 V, the output current is $10{\mu}A$, and the operating temperature is $20^{\circ}C$.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.79-86
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• 2002

This paper presents a low power scheduling and allocation algorithm for multiple supply voltage. The proposed supply voltage scheduling algorithm determines the control step to execute a possible the operation experimentally using another supply voltage level. Also, the switching activity using component library. and the supply voltage allocation method uses the graph coloring technique for low power, the proposed algorithm Proves the effect through various high level benchmark examples to adopt a multiple supply voltage scheduling algorithm for low power.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.11
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• pp.676-680
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• 2016

This paper describes a low voltage detection circuit used in the semiconductor chips. The circuit was composed of a detection part of the CMOS structure as three stages and two inverters. The output of the low voltage detection circuit become to 'high' from 'low', when the power supply voltage falls below 80%. When the power supply voltage is 5 V, it was detected at 4 V point. The proposed low voltage detection circuit can be easily applied only by changing the resister and the capacitor without structural change in a wide range of power supply voltage.

• ETRI Journal
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• v.34 no.5
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• pp.727-733
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• 2012

This paper demonstrates a new driving scheme that allows reducing the supply voltage of data drivers for low-power active matrix organic light-emitting diode (AMOLED) displays. The proposed technique drives down the data voltage range by 50%, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 75%. Because the gate voltage of a driving thin film transistor covers the same range as a conventional driving scheme by means of a level-shifting scheme, the low-data supply scheme achieves the equivalent dynamic range of OLED currents. The average power consumption of data drivers is reduced by 60% over 24 test images, and power consumption is kept below 25%.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.3
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• pp.211-219
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• 2014

This paper proposes a low voltage high current LLC resonant converter for Green PC. Green PC is composed of a lot of blade PCs, and it is a centralized system to manage them in computer center. Green PC should require that its power supplies have several characteristics such as low output voltage, high output current, and high power conversion efficiency. Conventional PSFB (Phase Shift Full Bridge) converter is usually used as DC/DC converter for computer power supply because it has high power conversion efficiency thanks to ZVS (Zero Voltage Switching) operation under middle and high load conditions. However, this converter has some problems such as large switching noise and limitation of ZVS operation under light load condition. In order to improve the performance of power supply for Green PC, a new power supply using popular high efficiency LLC resonant converter for low voltage and high current application is proposed in this paper. The proposed power supply has ZVS capability over the entire load range, thus resulting in good efficiency and high switching frequency. Experimental results verify the performance of the proposed power supply for Green PC using 2[kW] (19[V], 105[A]) rated prototype converter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.313-319
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• 2012

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-${\mu}m$ standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-${\mu}A$.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.3-11
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• 2002

This paper presents the trend of low voltage and high current technology for DC-DC converters. It can be said that the output voltage of the on-board power supply has been rapidly moving forward a low voltage in proportion to the minuteness of the semiconductors. As for as its speed is concerned, the change of the market situation seems to be faster than that of R&D for the low voltage and high current products put out by power supply manufacturers. Here, the present situation and the trend of non-isolated type step-down DC-DC converter and isolated type DC-DC converter called "Brick" will be taken up mainly from the fellowing point of view. -low voltage and high current keeping up with the current demand for the latest telecommunication networks and broadband. -build-up of the total solution for dispersion system power supply. In this paper, an explanation is given to mainly concerning to the newest products in the supplier's position.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.