• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 C
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• pp.1437-1439
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• 1999

This paper describes test method though low voltage power system implementation for high impedance fault relay test before its operation in real power system. Through this test, relay tested its function and algorithm. In this paper, we will provides test method using low voltage power system and its results.

• ETRI Journal
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• 제25권5호
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• pp.321-327
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• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권7호
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• 대한전자공학회논문지SD
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• 제41권9호
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• pp.85-95
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• 2004

최근 반도체 칩의 집적도가 올라가고 System-on-Chip(Soc)환경이 보편화되면서 Automatic Test Equipment(ATE)를 이용한 테스트 수행시 테스트 패턴의 크기 문제와 스캔체인에서의 전력 소모문제가 크게 부각되고 있다. 또한, 테스트 패턴 크기문제를 해결하기 위해 테스트 패턴을 압축하게 되면 테스트 패턴의 소모하는 전력량이 커지게 되어 저전력 테스트를 수행하는데 어려움이 있어 두 가지 문제를 해결할 수 없었다 본 논문에서는 이러한 문제점들을 동시에 해결하기 위해서 Run-length code를 기반으로 하여 저전력 테스트가 가능하면서 테스트 패턴의 크기도 줄일 수 있는 알고리즘을 제안하였다. 본 논문에서는 기존에 제시되었던 알고리즘과 비교ㆍ분석하는 실험을 통하여 이 알고리즘의 효율성을 보여주고 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.228-230
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• 2002

We present a new low power scan testing and test data compression method for System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full-scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.961-963
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• 2000

Most of the application standard of the low-voltage devices have applied one the IEC standard another the UL standard. European union applied the IEC60947-1 standard has not exceed 1000V a.c. or 1500V d.c.. Therefore. it is necessary to the low-voltage device has expended for rated operational voltage with our products. The export of European market shall be made for the CE-Marking in accordance with IEC60947-1 ( Low-voltage switchgear and controlgear). We shall be considered for the requirement with the IEC standard. In this time to study for power supply system at EU ( European union. At that time for design and development in order to the construction and test method among the study for the rated insulation voltage at less then 690V.

• Nuclear Engineering and Technology
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• 제51권4호
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• pp.1032-1036
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• 2019

When the equipment which is related to safety or important to power production is installed in nuclear power plant units (NPPs), verification of equipment Electromagnetic Susceptibility (EMS) must be performed. The low-frequency radiated magnetic field susceptibility (RS101) test is one of the EMS tests specified in U.S NRC (Nuclear Regulatory Commission) Regulatory Guide (RG) 1.180 revision 1. The RS101 test verifies the ability of equipment installed in close proximity to sources of large radiated magnetic fields to withstand them. However, RG 1.180 revision 1 allows for an exemption of the low-frequency radiated magnetic susceptibility (RS101) test if the safety-related equipment will not be installed in areas with strong sources of magnetic fields. There is no specific exemption criterion in RG 1.180 revision 1. EPRI TR-102323 revision 4 specifically provides a guide that the low-frequency radiated magnetic field susceptibility (RS101) test can be conservatively exempted for equipment installed at least 1 m away from the sources of large magnetic fields (>300 A/m). But there is no exemption criterion for equipment installed within 1 m of the sources of smaller magnetic fields (<300 A/m). Since some types of equipment radiating magnetic flux are often installed near safety related equipment in an electrical equipment room (EER) and main control room (MCR), the RS101 test exemption criterion needs to be reasonably defined for the cases of installation within 1 m. There is also insufficient data regarding the strength of magnetic fields that can be used in NPPs. In order to ensure confidence in the RS101 test exemption criterion, we measured the strength of low-frequency radiated magnetic fields by distance. This study is expected to provide an insight into the RS101 test exemption criterion that meets the RG 1.180 revision 1. It also provides a margin analysis that can be used to mitigate the influence of low-frequency radiated magnetic field sources in NPPs.

• 한국콘텐츠학회논문지
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• 제5권4호
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• pp.188-196
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• 2005

본 논문에서는 테스트 시간과 전력소모를 감축할 수 있는 새로운 테스트 데이터 압축 및 저전력 스캔 테스트 방법을 제안하였다. 제안된 방법은 수정된 스캔 셀 재배열과 하이브리드 적응적 부호화 방법을 사용하여 scan-in전력과 테스트 데이터 량을 줄였으며 하이브리드 테스트 데이터 압축방법은 Golomb Code와 런길이(run-length) 코드를 테스트 데이터내의 런(run) 길이에 따라서 적응적으로 적용하는 방법이다. 또한 scan-in 전력소모를 최소화하기 위해서 스캔 벡터내의 열 해밍거리를 이용하였다. ISCAS89 벤치마크 회로에 적용하여 실험한 결과, 모든 경우에 있어서 테스트 데이터 및 전력소모를 효율적으로 감소시켰으며 압축률은 17%-26%, 평균 전력소모는 8%-22%, 최고전력소모는 13%-60% 정도의 향상률을 보였다.

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.104-110
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• 2006

오늘날 시스템 온 칩 테스트에 있어서 많은 양의 테스트 데이터, 시간 및 전력 소모는 매우 중요한 문제이다. 이러한 문제들을 해결하기 위해서 본 논문은 새로운 테스트 데이터 압축 기술을 제안한다. 우선, 테스트 큐브 집합에 있는 돈 캐어 비트에 저전력 테스트를 위한 비트할당을 한다. 그리고, 비트할당이 된 저전력 테스트 데이터의 압축효율을 높이기 위해 이웃 비트 배타적 논리합 변환을 사용하여 변환한다. 최종적으로, 변환된 테스트 데이터는 효과적으로 압축됨으로써 테스트 장비의 저장공간과 테스트 데이터 인가시간을 줄일 수 있게 된다.

• KEPCO Journal on Electric Power and Energy
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• 제7권1호
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• pp.101-105
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• 2021

Encouragement of DER from Korean government with several policies boosts DER installation in power system. When the penetration of DER in the grid is getting high, loss of generation with break-away of DER by abnormal grid conditions should be considered, because loss of high generation causes abnormal low frequency and additional operations of protection system. Therefore, KEPCO where is Korean power utility is preparing improvement in regulations for DERs connected to the grid to support abnormal grid conditions such as low and high frequencies or voltages. This is called 'Ride Through' because the requirement is for DER to maintain grid connection during required periods when abnormal grid conditions occur. However, it is not easy to have a test for ride through capability in reality because emulation of abnormal grid conditions is not possible in real power system in operation. Also, it is not easy to have a study on grid effect when ride through capability fails with the same reason. PHILs (Power Hardware In the Loop System) makes it possible to analyze power system and hardware performance at once. Therefore, this paper introduces PHILs test methods and presents verification of ride through capability especially for low voltage grid conditions.