• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.65-72
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• 2013

This paper presents design methodology for Memristor-CMOS circuits and its application to primitive IPs design. We proposed a Memristor model and designed basic elements, Memristor AND/OR gates. The primitive IPs based on a Memristor-CMOS technology is proposed for a Memristive system design. The netlists of IPs are extracted from the layouts of Memristor-CMOS and is verified with SPICE-like Memristor model under $0.18{\mu}m$ CMOS technology. As a result, an example design Memristor-CMOS full adder has only 47.6 % of silicon area compare to the CMOS full-adder.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.1
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• pp.1-7
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• 2019

Recently, memristor (anion-based memristor) is referred to as the fourth circuit element which resistance state can be gradually changed by the electric pulse signals that have been applied to it. And the stored information in a memristor is non-volatile and also the resistance of a memristor can vary, through intermediate states, between high and low resistance states, by tuning the voltage and current. Therefore the memristor can be applied for analogue memory and/or learning device. Usually, memristive behavior is easily observed in the most transition metal oxide system, and it is explained by electrochemical migration motion of anion with electric field, electron scattering and joule heating. This paper reports the latest trends and issues of anion-based memristor.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.49-58
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• 2015

A floating type of memristor emulator which acts like the behavior of $TiO_2$ memristor has been developed. Most of existing memristor emulators are grounded type which is built disregarding the connectivity with other memristor or other devices. The developed memristor emulator is a floating type whose output does not need to be grounded. Therefore, the emulator is able to be connected with other devices and be utilized for the interoperability test with various other circuits. To prove the floating function of the proposed memristor emulator, a Wheatstone bridge is built by connecting 4 memristor emulators in series and parallel. Also this bridge circuit suggest that it is possible to weight calculation of the neural network synapse.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.10
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• pp.658-664
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• 2015

This paper presents an electrical feature analysis of hysteresis curves in memristor differential and intergral control circuit. After making macro model of the memristor device, electric characteristics of the model such as time analysis, frequency dependent DC I-V curves were performed by PSPICE simulation. Also, we made a circuit of memristor-capacitor based on nano-wired memristor device and analyzed the simulated PSPICE results. Finally, we proposed a memristor based differential or integral control circuit, analyzed hysteresis curve characteristic in the control circuit.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.98-107
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• 2016

An analytical comparison of a synthetic memristor emulator and a M-R mutator-based memristor emulator has been performed. Memristor is an electrical element with the characteristic of variable resistance. It is called the fourth fundamental electrical element following resistor, capacitor, and inductor. Memristor emulator is a circuit which implements the feature of variable resistance via the composition of various electrical devices. It is an essential circuit to study memristor characteristics during the time before it is commercially available. There are two representative memristor emulators depending upon their implementation methods. One is a memristor emulator which is synthesized via combining various electrical devices and the other one is M-R mutator-based memristor emulator implemented by extracting resistance from a nonlinear device. In this paper, implementation methods of these two memristor emulators are studied and their differences are investigated by analysing their characteristics.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.244.1-244.1
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• 2011

Memristors have been studied for many years due to better scalability than DRAMs and FLASH memories thus they are considered now as a strong candidate for future memories. To describe the electrical behavior of memristors, various memristor models have been developed. Especially, many kinds of window function have been used to express the non-linearity of memristors which are thought to cause different voltage-current relationships in memristors. In this paper, the previous memristor models with different window functions are compared and analyzed. This comparative study can be very useful in not only understanding the diversity in memristor's electrical behaviors but also developing memristor circuits. This work was financially supported by the SRC/ERC program of MOST/KOSEF (R11-2005-048-00000-0). The CAD tools were supported by the IC Design Education Center (IDEC), Korea.

• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.261-266
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• 2021

A simple memristor model is proposed for the neuromorphic system in the Simulation Program for Integrated Circuits Emphasis (SPICE). The memristive I-V characteristics with different voltage and frequencies were analyzed. And with the model, we configured a learning and inference system with 4 by 4 memristor array to show the practical use of the model. We examined the applicability by configuring the simplest neuromorphic circuit. The total simulation time for the proposed model was 18% lesser than that for the one-memristor model. When compared with more memristor models in a circuit, the time became even shorter.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.2
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• pp.1051-1058
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• 2014

This paper presents a Electrical characteristics of the Memristor device using the PSPICE for circuit analysis. After making macro model of the Memristor device for circuit analysis, electric characteristics of the model such as time analysis, frequency and DC analysis according to the input voltage were performed by PSPICE simulation. Also, we made simple circuits of memristor series and parallel structure and analyzed the simulated SPICE results. Finally, we made a memristor-capacitor (M-C) circuit. charge and discharge characteristics were analyzed. In case of input pulse signal of 250 Hz, the Memristor-capacitor circuit showed delay time of 0.6ms, rising time of 0.58 ms and falling time of 1.6 ms.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.5
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• pp.477-481
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• 2015

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.356-363
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• 2014

In this paper, we propose a new memristor-based crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.