• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.553-556
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• 2004

In this paper, we present a new efficient multi-level hardware/software partitioning algorithm for system-on-a-chip design. Originally the multi-level partitioning algorithm are proposed to enhance the performance of previous iterative improvement partitioning algorithm for large scale circuits. But when designing very complex and heterogeneous SoCs, the HW/SW partitioning decision needs to be made prior to refining the system description. In this paper, we present a new method, based on multi-level algorithm, which can cover SoC design. The different variants of algorithm are evaluated by a randomly generated test graph. The experimental results on test graphs show improvement average $9.85\%$ and $8.51\%$ in total communication costs over FM and CLIP respectively.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.4
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• pp.1693-1713
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• 2018

An important technique used by database administrators (DBAs) is to improve performance in decision-support workloads associated with a Star schema is multi-level partitioning. Queries will then benefit from performance improvements via partition elimination, due to constraints on queries expressed on the dimension tables. As the task of multi-level partitioning can be overwhelming for a DBA we are proposing a wizard that facilitates the task by calculating a partitioning scheme for a particular workload. The system resides completely on a client and interacts with the costing estimation subsystem of the query optimizer via an API over the network, thereby eliminating any need to make changes to the optimizer. In addition, since only cost estimates are needed the wizard overhead is very low. By using a greedy algorithm for search space enumeration over the query predicates in the workload the wizard is efficient with worst-case polynomial complexity. The technology proposed can be applied to any clustering or partitioning scheme in any database management system that provides an interface to the query optimizer. Applied to the Teradata database the technology provides recommendations that outperform a human expert's solution as measured by the total execution time of the workload. We also demonstrate the scalability of our approach when the fact table (and workload) size increases.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1995.11a
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• pp.79-88
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• 1995

Most works done so far have concentrated on developing data modeling techniques such as multi-level relation for data protection. These techniques, however, cannot be applied to practical area. This is because they require new queries or new architectures. In this paper, we propose a query processing technique for multi-level databases using horizontal partitioning and views, which does not need any change in database architecture and query language.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.4
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• pp.1188-1202
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• 2012

In this paper, we propose a new multi-scale connected coherence tree algorithm (MCCTA) by improving the connected coherence tree algorithm (CCTA). In contrast to many multi-scale image processing algorithms, MCCTA works on multiple scales space of an image and can adaptively change the parameters to capture the coarse and fine level details. Furthermore, we design a Multi-scale Connected Coherence Tree algorithm plus Spectral graph partitioning (MCCTSGP) by combining MCCTA and Spectral graph partitioning in to a new framework. Specifically, the graph nodes are the regions produced by CCTA and the image pixels, and the weights are the affinities between nodes. Then we run a spectral graph partitioning algorithm to partition on the graph which can consider the information both from pixels and regions to improve the quality of segments for providing image segmentation. The experimental results on Berkeley image database demonstrate the accuracy of our algorithm as compared to existing popular methods.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.338-346
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• 1987

This paper describes a method for verifying whether a given geometrical layout correcdtly reflects the original logic level description. The logic description extracted from layout data was directly compadred with the original logic diagram generated at logic level design stage where the logic diagram is represented as a weighted multi-place graph. The comparison is based on graph isomorphism and error messages(error categories and locations)are invoked if any difference is found between the two logic descriptions. An efficient partitioning algorithm which consists of two steps, candidate selection and equal weight partitioning procedure, enables the entire verification process to occur in O(n log n) time.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1771-1774
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• 2003

Image segmentation is very important technique as preprocessing. It is used for various applications such as object recognition, computer vision, object based image compression. In this paper, a method which segments the multidimensional image using a hierarchical histogram approach, is proposed. The hierarchical histogram approach is a method that decomposes the multi-dimensional situation into multi levels of 1 dimensional situations. It has the advantage of the rapid and easy calculation of the histogram, and at the same time because the histogram is applied at each level and not as a whole, it is possible to have more detailed partitioning of the situation.

• Asia pacific journal of information systems
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• v.20 no.2
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• pp.23-37
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• 2010

Conventional Support Vector Machines (SVMs) have been utilized as classifiers for binary classification problems. However, certain real world problems, including corporate bond rating, cannot be addressed by binary classifiers because these are multi-class problems. For this reason, numerous studies have attempted to transform the original SVM into a multiclass classifier. These studies, however, have only considered nominal classification problems. Thus, these approaches have been limited by the existence of multiclass classification problems where classes are not nominal but ordinal in real world, such as corporate bond rating and multiclass customer classification. In this study, we adopt a novel multiclass SVM which can address ordinal classification problems using ordinal pairwise partitioning (OPP). The proposed model in our study may use fewer classifiers, but it classifies more accurately because it considers the characteristics of the order of the classes. Although it can be applied to all kinds of ordinal multiclass classification problems, most prior studies have applied it to finance area like bond rating. Thus, this study applies it to a real world customer level classification case for implementing customer relationship management. The result shows that the ordinal multiclass SVM model may also be effective for customer level classification.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.133-136
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• 2003

In this paper, we propose a low bit-rate embedded video coding scheme with 3-D block partition in the wavelet domain. The proposed video coding scheme includes multi-level three dimensional dyadic wavelet decomposition, raster scanning within each subband, partitioning of blocks, and adaptive arithmetic entropy coding. Although the proposed video coding scheme is quite simple, it produces bit-streams with good features, including SNR scalability from the embedded nature. Experimental results demonstrate that the proposed video coding scheme is quite competitive to other good wavelet-based video coders in the literature.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.8
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• pp.1-11
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• 2012

The multi-code spread spectrum communication system, which spreads data bit stream by multiplexing orthogonal codes, can transmit data in high rate. However it needs the high-cost good linear amplifier because of the multi-level output signal. In order to overcome this drawback several systems making the amplitude of output signal constant with Walsh codes have been proposed. Recently constant amplitude pre-coded multi-code spread spectrum systems using extended m-sequence have been proposed. In this paper we consider an extended m-sequence based constant amplitude multi-code spread spectrum system with code set partitioning. By grouping the orthogonal codes into 4 subsets, not only is the computational complexity of the transceiver reduced but BER performance also improves. It has been shown that parity checking on four detected codes at the receiver can correct code detection error and result in BER performance enhancement. In this paper we propose a improved parity check receiver. We carried out computer simulation to verify feasibility of the proposed algorithm.