• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.496-496
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• 2000

We propose a neuron computer for tracking motion of particles in multi-dimensional space. The neuron computer is constructed of neural networks and their connections, which is a simplified model of the brain. The neuron computer is assemblage of neural networks, it includes a control unit, and the actions of the unit are represented by instructions. We designed a neuron computer to recognize and predict motion of particles. The recognition unit is constructed of neuron-array, encoder, and control part. The neuron-array is a model of the retina, and particles crease an image on the array, where the image is binary. The encoder picks one particle from the array, and translates the particle's location to Cartesian coordinates, which is scaled in [0, 1] intervals. Next, the encoder picks another particle, and does same process. The ordering and reduction of complex processes are executed by instructions. The instructions are held in the control part. The prediction unit is constructed of a multi-layer neural network and a feedback loop, where real time learning is executed. The particles' future locations are forecasted by coordinate values. The neuron computer can chase maximum 100 particles that take evasions.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.365-373
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• 2015

We propose a simple and compact thyristor-based neuron circuit. The thyristor exhibits bi-stable characteristics that can mimic the action potential of the biological neuron, when it is switched between its OFF-state and ON-state with the help of assist circuit. In addition, a method of inter-neuron connection with synaptic devices is proposed, using double current mirror circuit. The circuit utilizes both short-term and long-term plasticity of the synaptic devices by flowing current through them and transferring it to the post-synaptic neuron. The double current mirror circuit is capable of shielding the pre-synaptic neuron from the post synaptic-neuron while transferring the signal through it, maintaining the synaptic conductance unaffected by the change in the input voltage of the post-synaptic neuron.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.449-449
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• 2000

Many researchers have studied architectures for non-Neumann's computers because of escaping its bottleneck. To avoid the bottleneck, a neuron-based computer has been developed. The computer has only neurons and their connections, which are constructed of the learning. But still it has information processing facilities, and at the same time, it is like as a simplified brain to make inference; it is called "neuron-computer". No instructions are considered in any neural network usually; however, to complete complex processing on restricted computing resources, the processing must be reduced to primitive actions. Therefore, we introduce the instructions to the neuron-computer, in which the most important function is implications. There is an implication represented by binary-operators, but general implications for multi-value or fuzzy logics can't be done. Therefore, we need to use Lukasiewicz' operator at least. We investigated a neuron-computer having instructions for general implications. If we use the computer, the effective inferences base on multi-value logic is executed rapidly in a small logical unit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.383-390
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• 2014

This paper presents an excitatory CMOS neuron oscillator circuit design, which can synchronize two neuron-bursting patterns. The excitatory CMOS neuron oscillator is composed of CMOS neurons and CMOS excitatory synapses. And the neurons and synapses are connected into a close loop. The CMOS neuron is based on the Hindmarsh-Rose (HR) neuron model and excitatory synapse is based on the chemical synapse model. In order to fabricate using a 0.18 um CMOS standard process technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This full-chip integration minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot. The experimental results demonstrate that the proposed excitatory CMOS neuron oscillator performs the expected waveforms with scaled time and amplitude. The active silicon area of the fabricated chip is $1.1mm^2$ including I/O pads.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.755-759
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• 2014

We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has short-term and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.06a
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• pp.395-398
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• 1998

In this paper, a method for the improvement of learning speed and convergence rate was proposed applied it to physiological neural structure with the advantages of artificial neural networks and fuzzy theory to physiological neuron structure, To compare the proposed method with conventional the single layer perception algorithm, we applied these algorithms bit parity problem and pattern recognition containing noise. The simulation result indicated that our learning algorithm reduces the possibility of local minima more than the conventional single layer perception does. Furthermore we show that our learning algorithm guarantees the convergence.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.658-663
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• 2015

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrate-and-Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.174-179
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• 2017

We designed the CMOS analog integrate and fire (I&F) neuron circuit for driving memristor based on resistive-switching random access memory (RRAM). And we fabricated the RRAM device that have $HfO_2$ switching layer using atomic layer deposition (ALD). The RRAM device has gradual set and reset characteristics. By spice modeling of the synaptic device, we performed circuit simulation of synaptic device and CMOS neuron circuit. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, two inverters for pulse generation, a refractory part, and finally a feedback part for learning of the RRAM. We emulated the spike-timing-dependent-plasticity (STDP) characteristic that is performed automatically by pre-synaptic pulse and feedback signal of the neuron circuit. By STDP characteristics, the synaptic weight, conductance of the RRAM, is changed without additional control circuit.

• Journal of the Korea Society of Computer and Information
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• v.4 no.2
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• pp.27-38
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• 1999

This paper proposes a high speed digital neuron processor which uses the residue number system, making the high speed operation possible without carry propagation,. Consisting of the MAC(Multiplier and with Accumulator) operation unit, quotient operation unit and sigmoid function operation unit, the neuron processor is designed through 0.8$\mu$m CMOS fabrication. The result shows that the new implemented neuron processor can run at the speed of 19.2 nSec and the size can be reduced to 1/2 compared to the neuron processor implemented by the real number operation unit.

• Journal of information and communication convergence engineering
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• v.1 no.3
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• pp.104-108
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• 2003

A biologically inspired fuzzy multilayer perceptron is proposed in this paper. The proposed algorithm is established under consideration of biological neuronal structure as well as fuzzy logic operation. We applied this suggested learning algorithm to benchmark problem in neural network such as exclusive OR and 3-bit parity, and to digit image recognition problems. For the comparison between the existing and proposed neural networks, the convergence speed is measured. The result of our simulation indicates that the convergence speed of the proposed learning algorithm is much faster than that of conventional backpropagation algorithm. Furthermore, in the image recognition task, the recognition rate of our learning algorithm is higher than of conventional backpropagation algorithm.