• Journal of the Korean Ceramic Society
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• v.47 no.5
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• pp.419-425
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• 2010

In order to examine the P.H.C pile raw material using glass forming ceramic. The used materials is ordinary portland cement, waste TFT-LCD glass powder and reactive agent(Ca$(OH)_2$). The first experiment is characteristics analysis of the waste TFT-LCD glass powder, For the second experiment is mortar and concrete compressive strength for using of the concrete file raw material for waste TFT-LCD glass powder. The results of experiment showed that the substitution ratio of 10% waste TFT-LCD glass powder and 1% reactive agent(Ca$(OH)_2$) was excellent at a point of view for the physical characteristic. The study's most important finding is that the recycling of waste TFT-LCD glass powder.

• Korean Journal of Materials Research
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• v.19 no.1
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• pp.33-36
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• 2009

Inorganic-organic composite thin-film-transistors (TFTs) of ZnO nanowire/Poly(3-hexylthiophene) (P3HT) were investigated by changing the nanowire densities inside the composites. Crystalline ZnO nanowires were synthesized via an aqueous solution method at a low temperature, and the nanowire densities inside the composites were controlled by changing the ultrasonifiaction time. The channel layers were prepared with composites by spin-coating at 2000 rpm, which was followed by annealing in a vacuum at $100^{\circ}C$ for 10 hours. Au/inorganic-organic composite layer/$SiO_2$ structures were fabricated and the mobility, $I_{on}/I_{off}$ ratio, and threshold voltage were then measured to analyze the electrical characteristics of the channel layer. Compared with a P3HT TFT, the electrical properties of TFT were found to be improved after increasing the nanowire density inside the composites. The mobility of the P3HT TFT was approximately $10^{-4}cm^2/V{\cdot}s$. However, the mobility of the ZnO nanowire/P3HT composite TFT was increased by two orders compared to that of the P3HT TFT. In terms of the $I_{on}/I_{off}$ ratio, the composite device showed a two-fold increase compared to that of the P3HT TFT.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.3
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• pp.279-284
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• 2014

This paper proposes a novel OLED pixel circuit to compensate the threshold voltage variation of p-channel low temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed 5-TFT OLED pixel circuit consists of 4 switching TFTs, 1 OLED driving TFT and 1 capacitor. One frame of the proposed pixel circuit is divided into initialization period, threshold voltage sensing and data programming period, data holding period and emission period. SmartSpice simulation results show that the maximum error rate of OLED current is -4.06% when the threshold voltage of driving TFT varies by ${\pm}0.25V$ and that of OLED current is 9.74% when the threshold voltage of driving TFT varies by ${\pm}0.50V$. Thus, the proposed 5T1C pixel circuit can realize uniform OLED current with high immunity to the threshold voltage variation of p-channel poly-Si TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.9
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2002-2007
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• 1999

In this paper, the n-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) on glass were investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. It is done to decide to be applied on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 2, 10, 25$\mu\textrm{m}$ of channel length, the field effect mobilities are 111, 126 and 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus, the poly-Si TFT’s used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate display panel and peripheral circuit on a large glass substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.11
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• pp.869-873
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• 2001

The effects of alternate bias stress on p-channel poly-Si TFT\`s has been systematically investigated. We alternately applied positive and negative bias stress on p-channel poly-Si TFT\`s, device Performance(V$\_$th/, g$\_$m/, leakage current, S-slope) are alternately appeared to be increasing and decreasing. It has been shown that device performance degrade under the negative bias stress while improve under the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ interface under alternate bias stress.

• Korean Chemical Engineering Research
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• v.48 no.6
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• pp.737-740
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• 2010

High leakage current and threshold voltage shift(${\Delta}Vth$) are demerits of a-Si:H TFT. These characteristics are influenced by gate insulator and active layer film quality, surface roughness, and process conditions. The purpose of this investigation is to improve off current($I_{off}$) and ${\Delta}V_{th}$ characteristics. Nitrogen-rich deposition condition was applied to gate insulator, and hydrogen-rich deposition condition was applied to active layer to reduce electron trap site and improve film density. $I_{off}$ improved from 1.01 pA to 0.18 pA at $65^{\circ}C$, and ${\Delta}V_{th}$ improved from -1.89 V to 1.22 V.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.459-462
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• 2006

In this paper, we proposed a novel TFT-LCD pixel structure to compensate ${\Delta}V_p$, which is a maximum value of 1.82V in conventional pixel structure without compensation. We achieved a maximum value of 60mV in proposed pixel structure by integrating a dummy switch TFT in each pixel. The proposed TFT-LCD pixel structure with a remarkably reduced ${\Delta}V_p$ allows ultra high picture quality AMLCDs.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.53-58
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• 1998

A buried channel poly-Si TFT (BCTFT) for application of high performance integrated circuits has been proposed and fabricated. BCTFT has unique features, such as the moderately-doped buried channel and counter-doped body region for conductivity modulation, and the fourth terminal entitled back bias for preventing kink effect. The n-type and p-type BCTFT exhibits superior performance to conventional poly-Si TFT in ON-current and field effect mobility due to moderate doping at the buried channel. The OFF-state leakage current is not increased because the carrier drift is suppressed by the p-n junction depletion between the moderately-doped buried channel and the counter-doped body region.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.324-327
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• 2000

In this paper, the effects of negative and positive bias stress on p-channel poly-Si TFT's fabricated by excimer laser annealing have been investigated After positive and negative bias stress, transcon-ductance(g$_{m}$) is increased because of a reduction of the effective channel length due to the injected electron in the gate oxide. In the positive bias stress, the injection of hole is appeared after stress time of 3600sec and g$_{m}$ is decreased. On the other hand, the gate voltage at the maximum g$_{m}$, S-swing and threshold voltage(V$_{th}$) are decreased because of the interface state generation due to the injection of electrons into the gate oxide.e.ide.e.