• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.312-317
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• 2015

In this paper, the RF characteristics of multi-finger MOSFETs were improved by decreasing the parasitic capacitance in spite of increased gate resistance in a 90-nm CMOS technology. Two types of device structures were designed to compare the parasitic capacitance in the gate-to-source ($C_{gs}$) and gate-to-drain ($C_{gd}$) configurations. The radio frequency (RF) performance of multi-finger MOSFETs, such as cut-off frequency ($f_T$) and maximum-oscillation frequency ($f_{max}$) improved by approximately 10% by reducing the parasitic capacitance about 8.2% while maintaining the DC performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.653-657
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• 2015

A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.

• Journal of IKEEE
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• v.22 no.1
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• pp.185-188
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• 2018

This paper describes the parasitic capacitance modeling according to the coil structure, section bobbin and winding method for hybrid choke coil with reduced parasitic capacitance capable of the EMI attenuation of broad bands from lower frequency to higher frequency applied in the EMI attenuation filter of LED-TV SMPS. Especially, the hybrid choke coil with reduced parasitic capacitance($C_p$) proposed in this paper can reduces the parasitic capacitance($C_p$) by adopting the winding methods of rectangular copper wire, compared to the conventional common mode choke coil with the winding method of automatic type. The first resonant frequency of the proposed hybrid choke coil has a tendency to increase as the parasitic capacitance is smaller and its impedance characteristics, especially in the high frequency bands, improves as the first resonant frequency increases. In the future, the proposed hybrid choke coil with reduced parasitic capacitance shows it can be actually utilized in not only LED-TV SMPS but also various applications such as LED Lighting, Note-PC Adapter, and so forth.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.137-143
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• 2015

This paper presents the intra capacitance modeling based on the winding method and section bobbin for CM choke capable of EMI attenuation of broad bands from lower to higher frequency bands and high frequency type common-mode choke capable of EMI attenuation of high frequency band used in the EMI Block of LED-TV SMPS. The case of high frequency type CM choke can be explained by the parasitic capacitance of three types of CM choke. The winding method of section bobbin type is smaller than the others. The first resonant frequency of the proposed CM choke tends to increase as the parasitic capacitance becomes small and its impedance characteristics improved performance as the first resonant frequency increases. The CM chokes of the proposed section bobbin type shows that in the future, the method may have practical use in LED/LCD-TV SMPS and in several applications, such as LED lighting, adapters, and so on.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.4
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• pp.522-530
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• 2018

This study proposes the mitigation method of shaft voltage by varying the parasitic capacitance. First, the shaft voltage explained. Second, the parasitic capacitances causing shaft voltage are analyzed respect to geometry of motor and windings. Then, the equivalent circuit is established to obtain the shaft voltage and output torque characteristic and develope appropriate motor structure. Finally, simulation and experiment are conducted to verify that modified motor suppress the shaft voltage. This novel model does not require additional hardware.

• Journal of Industrial Technology
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• v.29 no.B
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• pp.187-191
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• 2009

Recently, we have used LEDs to illumination because it has a high luminous efficiency and prolong lifespan. However the light power and lifetime is reduced by junction temperature increment of LED. So it is important to measure the junction temperature accurately. In case of using a electrical method measuring junction temperature of LED. Temperature measurement errors are spontaneously generated because of a parasitic capacitances in LED. In this paper, we proposed a method that reducing LED's parasitic capacitance effects for electrical measurement. It was demonstrated by the experimental result that is more correct than established method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.7 no.5
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• pp.395-407
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• 1996

In this paper, we describe the crossover of the parasitic capacitance at the interconnections for the system miniature, analyse ground capacitance and mutual capacitance due to actually coupled line in the ICs or MCMs. From the results of deviding interconnection line with infinite parts, using Green's function with image charge method and moments, we could obtain 70% decrease of system runtime parasitic inductance because of simplicity of transforming formular.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• Journal of Power Electronics
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• v.18 no.4
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.