• Title/Summary/Keyword: phase modulator

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Variable and Flexible Optical Frequency Comb Source using Dual Mach Zehnder Modulator and Phase Modulator

  • Naveed, Abbas;Choi, Bong-Soo;Tran, ThanhTuan;Seo, Dongsun
    • Journal of IKEEE
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    • v.20 no.4
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    • pp.385-391
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    • 2016
  • We demonstrated experimentally a variable optical frequency comb source using a cascaded dual parallel Mach Zehnder modulator (DPMZM) and a phase modulator (PM). With this simple configuration and applying low drive voltages, we generated variable comb source composed of spectral lines 3, 5, 7, 9 and 11 with 10-GHz frequency spacing, also generated 2 and 3 spectral lines with 20 GHz frequency spacing. The generated comb source maintains high spectral coherence across the entire bandwidth with good spectral flatness (within 1-dB for 2, 3, 5, 7 comb lines, within 2-dB for 9-comb lines and within 3-dB for 11 comb lines). The flat and variable comb source is mainly achieved by manipulating 6 operating parameters of DPMZM, setting RF amplifier gain, connected at phase modulator and phase shifters. Hence the method is simple and offers great flexibility in achieving flat and variable comb spectrum, which is experimentally demonstrated. This brings advantages of power efficiency due to low driving voltages, simplicity and cost effectiveness to the system.

Increased Effective Capacitance with Current Modulator in PLL (Current Modulator를 이용하여 유효커패시턴스를 크게 하는 위상고정루프)

  • Kim, Hye-Jin;Choi, Young-Shig
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.4
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    • pp.136-141
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    • 2016
  • A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

A Design of IQ Modulator for Direct Carrier Modulation Systems (직접 반송파 변조 시스템을 위한 IQ 변조기 설계)

  • Mun, Tae-Su;Kim, Phirun;Jeong, Yong-Chae
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.9
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    • pp.847-851
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    • 2011
  • In this paper, a novel IQ modulator that precisely controls the magnitude and phase of input signals is proposed. The proposed IQ modulator consists of low phase deviation attenuators, a splitter, and a combiner. In order to overcome the phase deviation characteristics found in conventional attenuators, a novel phase compensation technique has been adopted and mathematically analyzed. Linear vector arrays along the center point with large magnitude output signal variations in a full $360^{\circ}$ phase control are achieved on a polar plane by the proposed IQ modulator.

A Novel Measurement Approach for the Half-wave Voltage of Phase Modulator based on PM-MZI Photonic Link

  • Xianghua, Li;Chun, Yang;Quanyi, Ye;Yuhua, Chong;Zhenghua, Zhou
    • Journal of the Optical Society of Korea
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    • v.18 no.3
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    • pp.288-291
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    • 2014
  • This paper presents a new method for measuring the half-wave voltage $V_{\pi}$ of an electro-optic phase modulator based on a phase-modulated photonic link with interferometric demodulation. By using this method, the $V_{\pi}$ can be obtained with the RF voltage amplitude input required to achieve 1-dB gain compression of link and the differential delay of a Mach-Zehnder interferometer. We measure the $V_{\pi}$ of a commercial phase modulator by using the presented method and the carrier/the first sideband intensity ratio method. Furthermore, we compare the two measurements with the typical value provided by the manufacturer. The experiment shows that this novel measurement method is feasible, straightforward, and accurate.

Binary-phase Complex Spatial Light Modulators Driven by Mirror Symmetry

  • Choi, Minho;Choi, Jaewu
    • Current Optics and Photonics
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    • v.5 no.3
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    • pp.261-269
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    • 2021
  • Binary-phase complex spatial light modulators (BP-C-SLMs) are proposed and simulated. This study shows that bottom-top mirror-symmetrical uniaxial systems between two orthogonal polarizers allow one to construct BP-C-SLMs. BP-C-SLMs double the information-handling capacity per pixel, compared to the conventional amplitude-only spatial light modulators (A-SLMs), as well as being simply implemented with a single spatial light modulator (SLM), rather than a combination of an A-SLM and a binary-phase SLMs. Under limited conditions, BP-C-SLMs can control only the amplitude in single-phase space, and act as A-SLMs.

GaAs/AlGaAs MQW waveguide phase modulator with optical bistability (광쌍안정을 갖는 GaAs/AlGaAs MQW 도파로형 위상 광변조기)

    • Korean Journal of Optics and Photonics
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    • v.7 no.3
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    • pp.280-286
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    • 1996
  • This paper describes operation mechanism of a novel optical waveguide phase modulator with optical bistability characteristics by self electro-optic effect. The fabricated device structure is an optical waveguide modulator, using a refractive index change by an applied electric field, parallel integrated with SEED with an electrical bistability. GaAs/AlGaAs MQW is used as the core layer of the waveguide modulator and the absorption layer of SEED. The absorbed optical power in SEED changes the diode voltage and controls the optical power propagating through the waveguide phase modulator. Optical bistability of waveguide phase modulator is experimentally obtained by using electrical bistability of SEED. Compared to other waveguide modulators, the proposed one has an asset that the lowest optical power is required to generate optical bistability.

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Increased Effective Capacitance in PLL (유효 커패시턴스를 증가를 구현한 소형 위상고정루프)

  • Ahn, Sung-Jin;Choi, Young-Shig
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.05a
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    • pp.698-701
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    • 2016
  • A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.

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Key Phase Mask Updating Scheme with Spatial Light Modulator for Secure Double Random Phase Encryption

  • Kwon, Seok-Chul;Lee, In-Ho
    • Journal of information and communication convergence engineering
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    • v.13 no.4
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    • pp.280-285
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    • 2015
  • Double random phase encryption (DRPE) is one of the well-known optical encryption techniques, and many techniques with DRPE have been developed for information security. However, most of these techniques may not solve the fundamental security problem caused by using fixed phase masks for DRPE. Therefore, in this paper, we propose a key phase mask updating scheme for DRPE to improve its security, where a spatial light modulator (SLM) is used to implement key phase mask updating. In the proposed scheme, updated key data are obtained by using previous image data and the first phase mask used in encryption. The SLM with the updated key is used as the second phase mask for encryption. We provide a detailed description of the method of encryption and decryption for a DRPE system using the proposed key updating scheme, and simulation results are also shown to verify that the proposed key updating scheme can enhance the security of the original DRPE.

Design of Fractional-N Frequency Synthesizer with Delta-Sigma Modulator for Wireless Mobile Communications (Delta-Sigma Modulator를 이용한 무선이동통신용 Fractional-N 주파수합성기 설계)

  • Park, Byung-Ha
    • Journal of IKEEE
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    • v.3 no.1 s.4
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    • pp.39-49
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    • 1999
  • This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

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Polar Transmitter with Differential DSM Phase and Digital PWM Envelope

  • Zhou, Bo;Liu, Shuli
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.3
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    • pp.313-321
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    • 2014
  • A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.