• 전기전자학회논문지
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• 제20권4호
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• pp.385-391
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• 2016

We demonstrated experimentally a variable optical frequency comb source using a cascaded dual parallel Mach Zehnder modulator (DPMZM) and a phase modulator (PM). With this simple configuration and applying low drive voltages, we generated variable comb source composed of spectral lines 3, 5, 7, 9 and 11 with 10-GHz frequency spacing, also generated 2 and 3 spectral lines with 20 GHz frequency spacing. The generated comb source maintains high spectral coherence across the entire bandwidth with good spectral flatness (within 1-dB for 2, 3, 5, 7 comb lines, within 2-dB for 9-comb lines and within 3-dB for 11 comb lines). The flat and variable comb source is mainly achieved by manipulating 6 operating parameters of DPMZM, setting RF amplifier gain, connected at phase modulator and phase shifters. Hence the method is simple and offers great flexibility in achieving flat and variable comb spectrum, which is experimentally demonstrated. This brings advantages of power efficiency due to low driving voltages, simplicity and cost effectiveness to the system.

• 전자공학회논문지
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• 제53권4호
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• pp.136-141
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• 2016

본 논문에서는 Current Modulator를 이용하여 루프 필터 커패시턴스 유효 용량을 배가 시켜 칩 크기를 줄일 수 있는 위상 고정루프를 제안하였다. 제안된 위상고정루프에서는 Current Modulator로 루프 필터의 커패시턴스 유효 용량을 배가 시켜 루프 필터 커패시터 크기를 1/10로 줄였다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 기존 구조와 같은 잡음 특성과 위상고정 시간을 보여주었다.

• 한국전자파학회논문지
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• 제22권9호
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• pp.847-851
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• 2011

본 논문에서는 입력 신호의 진폭과 위상을 미세 조정할 수 있는 새로운 IQ 변조기를 제안하였다. 제안된 IQ 변조기는 저위상 편차 감쇠기, 분배기, 그리고 결합기로 구성되어 있다. 기존 감쇠기의 위상 편차 특성을 극복하기 위한 새로운 위상 보상 기술을 사용하였고, 이를 수식적으로 분석하였다. 제안하는 IQ 변조기를 통하여 완전한 $360^{\circ}$의 위상 조정과 동시에 입력 신호의 큰 진폭 조정이 가능하며, 극좌표계의 중심점을 지나는 선형적인 IQ신호 배열을 구현하였다.

• Journal of the Optical Society of Korea
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• 제18권3호
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• pp.288-291
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• 2014

This paper presents a new method for measuring the half-wave voltage $V_{\pi}$ of an electro-optic phase modulator based on a phase-modulated photonic link with interferometric demodulation. By using this method, the $V_{\pi}$ can be obtained with the RF voltage amplitude input required to achieve 1-dB gain compression of link and the differential delay of a Mach-Zehnder interferometer. We measure the $V_{\pi}$ of a commercial phase modulator by using the presented method and the carrier/the first sideband intensity ratio method. Furthermore, we compare the two measurements with the typical value provided by the manufacturer. The experiment shows that this novel measurement method is feasible, straightforward, and accurate.

• Current Optics and Photonics
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• 제5권3호
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• pp.261-269
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• 2021

Binary-phase complex spatial light modulators (BP-C-SLMs) are proposed and simulated. This study shows that bottom-top mirror-symmetrical uniaxial systems between two orthogonal polarizers allow one to construct BP-C-SLMs. BP-C-SLMs double the information-handling capacity per pixel, compared to the conventional amplitude-only spatial light modulators (A-SLMs), as well as being simply implemented with a single spatial light modulator (SLM), rather than a combination of an A-SLM and a binary-phase SLMs. Under limited conditions, BP-C-SLMs can control only the amplitude in single-phase space, and act as A-SLMs.

• 한국광학회지
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• 제7권3호
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• pp.280-286
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• 1996

본 논문에서는 자기 전광 효과를 이용하여 광쌍안정을 갖는 새로운 형태의 도파로형 광변조기의 동작 특성에 관하여 논하였다. 제작된 소자는 전계의 세기에 따른 굴절률의 변화를 이용하는 위상 변조형 광변조기와 전기적 쌍안정성을 갖는 수광 소자가 병렬로 연결된 구조로 되어 있다. 광도파로층과 수광 소자의 흡수층은 GaAs/AlGaAs 다중 양자 우물층을 사용하였다. 수광 소자에 흡수되는 광의 세기에 따라 변하는 다이오드 전압은 도파로형 광변조기를 통과하는 광의 세기를 조절하며 SEED의 전기적 쌍안정을 이용하여 도파로형 광변조기의 광쌍안정을 얻을 수 있었다. 본 논문에서 제안된 광변조기는 기존의 도파로형 광변조기에 비해 낮은 입력광에서도 광안쌍정을 갖는 장점을 갖는다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.698-701
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• 2016

본 논문에서는 Current Modulator를 이용하여 루프 필터 커패시턴스 유효 용량을 배가 시켜 칩 크기를 줄일 수 있는 위상고정루프를 제안하였다. 제안된 위상고정루프에서는 Current Modulator로 루프 필터의 커패시턴스 유효 용량을 배가 시켜 루프 필터 커패시터 크기를 1/10로 줄였다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 기존 구조와 같은 잡음 특성과 위상고정 시간을 보여주었다.

• Journal of information and communication convergence engineering
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• 제13권4호
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• pp.280-285
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• 2015

Double random phase encryption (DRPE) is one of the well-known optical encryption techniques, and many techniques with DRPE have been developed for information security. However, most of these techniques may not solve the fundamental security problem caused by using fixed phase masks for DRPE. Therefore, in this paper, we propose a key phase mask updating scheme for DRPE to improve its security, where a spatial light modulator (SLM) is used to implement key phase mask updating. In the proposed scheme, updated key data are obtained by using previous image data and the first phase mask used in encryption. The SLM with the updated key is used as the second phase mask for encryption. We provide a detailed description of the method of encryption and decryption for a DRPE system using the proposed key updating scheme, and simulation results are also shown to verify that the proposed key updating scheme can enhance the security of the original DRPE.

• 전기전자학회논문지
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• 제3권1호
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.