• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.3
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• pp.235-241
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• 2020

In this paper, we propose the bus/bypass synchronization phase lock loop (B-Sync PLL) method using each phase voltage controller of a parallel UPS inverter. The B-Sync PLL included in each phase voltage control system of parallel UPS inverters has the transient response and the phase synchronization error at grid normal or blackout. The validity of this method is verified by simulation and experiment. As a result, the parallel UPS inverters using the proposed method confirmed that the output phase was continuously synchronized when a grid blackout, improving the transient response characteristics for stable load power supply and equal load sharing.

• Journal of electromagnetic engineering and science
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• v.5 no.1
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• pp.26-30
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• 2005

It is important to know phase offsets of PN(Pseudo Noise) sequences in spread spectrum communications since the acquisition is equivalent to making a phase offset between a receiving PN sequence and a PN sequence of local PN generator be identical. In this paper, a phase offset enumeration method for PN sequences with error detection, and its application to the synchronization are proposed. The phase offset enumeration for an n-tuple PN sequence and its error detection are performed when one period of the sequence is received. Once the phase offset of the receiving sequence is calculated, we can easily accomplish the synchronization by initializing shift registers of a local PN generator according to the phase offset value. The mean acquisition time performance of the proposed scheme was derived analytically. Since this synchronization scheme can be realized by using simple circuit and acquires very rapid acquisition in high SNR but shows performance degradation in low SNR, it can be especially useful in indoor and office environments.

• ETRI Journal
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• v.34 no.2
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• pp.175-183
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• 2012

Conventional synchronization algorithms for impulse radio require high-speed sampling and a precise local clock. Here, a phase-locked loop (PLL) scheme is introduced to acquire and track periodical impulses. The proposed impulse PLL (iPLL) is analyzed under an ideal Gaussian noise channel and multipath environment. The timing synchronization can be recovered directly from the locked frequency and phase. To make full use of the high harmonics of the received impulses efficiently in synchronization, the switching phase detector is applied in iPLL. It is capable of obtaining higher loop gain without a rise in timing errors. In different environments, simulations verify our analysis and show about one-tenth of the root mean square errors of conventional impulse synchronizations. The developed iPLL prototype applied in a high-speed ultra-wideband transceiver shows its feasibility, low complexity, and high precision.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.2891-2903
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• 2020

Phase-generated carrier (PGC) demodulation algorithm is the main demodulation methods in Fiber-optic interferometric sensors (FOISs). The conventional PGC demodulation algorithms are influenced by the carrier phase delay between the interference signal and the carrier signal. In this paper, an automatic carrier phase delay synchronization (CPDS) algorithm based on orthogonal phase-locked technique is proposed. The proposed algorithm can calculate the carrier phase delay value. Then the carrier phase delay can be compensated by adjusting the initial phase of the fundamental carrier and the second-harmonic carrier. The simulation results demonstrate the influence of the carrier phase delay on the demodulation performance. PGC-Arctan demodulation system based on CPDS algorithm is implemented on SoC. The experimental results show that the proposed algorithm is able to obtain and eliminate the carrier phase delay. In comparison to the conventional demodulation algorithm, the signal-to-noise and distortion ratio (SINAD) of the proposed algorithm increases 55.99dB.

• Journal of Power Electronics
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• v.14 no.3
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• pp.608-620
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• 2014

In this paper, an adaptive neural phase-locked loop (AN-PLL) based on adaptive linear neuron is proposed for grid-connected doubly fed induction generator (DFIG) synchronization. The proposed AN-PLL architecture comprises three stages, namely, the frequency of polluted and distorted grid voltages is tracked online; the grid voltages are filtered, and the voltage vector amplitude is detected; the phase angle is estimated. First, the AN-PLL architecture is implemented and applied to a real three-phase power supply. Thereafter, the performances and robustness of the new AN-PLL under voltage sag and two-phase faults are compared with those of conventional PLL. Finally, an application of the suggested AN-PLL in the grid-connected DFIG-decoupled control strategy is conducted. Experimental results prove the good performances of the new AN-PLL in grid-connected DFIG synchronization.

• The Journal of Natural Sciences
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• v.9 no.1
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• pp.75-81
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• 1997

The method of synchronization by feedbacking a signal of master system to a corresponding variable of slave system is applied to the Lorenz which is autonomous system. The two Lorenz systems are synchronized and the synchronization occurs when the consisting of the variable differences of the two systems generates infinite period of laminar phase. The characteristics of synchronization is analyzed in time series and phase spaces.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.1
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• pp.14-22
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• 1998

The Mathematic model of bit synchronization charge-pump Phase Locked Loop (PLL) is presented which takes into account the aperiodic reference pulses and the leakage current of the loop filter. We derive theoreitcal static phase error, overload and stability of bit synchronization charge-pump PLL using presented model and compare it with one of the conventional charge-pump PLL model. We can analysis bit synchronization charge-pump PLL exactly because our model takes into account the leakage current of the loop filter and aperiodic input data which are the charateristics of bit synchronization charge-pump PLL. We also verify it using HSPICE simulation with a bity synchronizer circuit.

• Journal of IKEEE
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• v.11 no.4
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• pp.322-330
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• 2007

Recent advances in wireless networks and low-cost, low-power design have led to active research in large-scale networks of small, wireless, low power sensors and actuators, In large-scale networks, lots of timing-synchronization protocols already exist (such as NTP, GPS), In ad-hoc networks, especially wireless sensor networks, it is hard to synchronize all nodes in networks because it has no infrastructure. In addition, sensor nodes have low-power CPU (it cannot perform the complex computation), low batteries, and even they have to have active and inactive section by periods. Therefore, new approach to time synchronization is needed for wireless sensor networks, In this paper, I propose Energy-Efficient Time Synchronization (EETS) protocol providing network-wide time synchronization in wireless sensor networks, The algorithm is organized two phase, In first phase, I make a hierarchical tree with sensor nodes by broadcasting "Level Discovery" packet. In second phase, I synchronize them by exchanging time stamp packets, And I also consider send time, access time and propagation time. I have shown the performance of EETS comparing Timing-sync Protocol for Sensor Networks (TPSN) and Reference Broadcast Synchronization (RBS) about energy efficiency and time synchronization accuracy using NESLsim.

• The Journal of the Acoustical Society of Korea
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• v.24 no.3E
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• pp.109-114
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• 2005

In this paper, we present a phase coherent all-digital transceiver for underwater acoustic communication, which allows the system to reduce complexity and increase robustness in time variant underwater environments. It is designed in the digital domain except for transducers and amplifiers and implemented by using a multiple digital signal processors (DSPs) system. For phase coherent reception, conventional systems employed phase-locked loop (PLL) and delay-locked loop (DLL) for synchronization, but this paper suggests a frame synchronization scheme based on the quadrature receiver structure without using phase information. We show experimental results in the underwater anechoic basin at MOERI. The results show that the adaptive equalizer compensates frame synchronization error and the correction capability is dependent on the length of equalizer.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.2
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• pp.39-50
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• 2008

Developing computational methods for identifying cell cycle-regulated genes has been one of important topics in systems biology. Most of previous methods consider the periodic characteristics of expression signals to identify the cell cycle-regulated genes. However, we assume that cell cycle-regulated genes are relatively active having relatively many interactions with each other based on the underlying cellular network. Thus, we are motivated to apply the theory of multivariate phase synchronization to the cell cycle expression analysis. In this study, we apply the method known as "Self-Organizing Maps with statistical Phase Synchronization (SOMPS)", which is the combination of self-organizing map and multivariate phase synchronization, producing several subsets of genes that are expected to have interactions with each other in their subset (Kim, 2008). Our evaluation experiments show that the SOMPS algorithm is able to detect cell cycle-regulated genes as much as one of recently reported method that performs better than most existing methods.