• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.78-84
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• 2012

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.201-207
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• 2012

Currently, NAND Flash memory has been widely used in consumer storage devices due to its non-volatility, stability, economical feasibility, low power usage, durability, and high density. However, a high capacity of NAND flash memory causes the high power consumption and the low performance. In the convention memory research, a hierarchical filter mechanism can archive an effective performance improvement in terms of the power consumption. In order to attain the best filter structure for NAND flash memory, we selected a direct-mapped filter, a victim filter, a fully associative filter and a 4-way set associative filter for comparison in the performance analysis. According to the results of the simulation, the fully associative filter buffer with a 128byte fetching size can obtain the bet performance compared to another filter structures, and it can reduce the energy*delay product(EDP) by about 93% compared to the conventional NAND Flash memory.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.25-32
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• 2014

In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

• Journal of the Korea Society of Computer and Information
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• v.21 no.9
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• pp.1-9
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• 2016

Recent embedded processors employ set-associative L1 instruction cache to improve the performance. The energy consumption in the set-associative L1 instruction cache accounts for considerable portion in the embedded processor. When an instruction is required from the processor, all ways in the set-associative instruction cache are accessed in parallel. In this paper, we propose the technique to reduce the energy consumption in the set-associative L1 instruction cache effectively by accessing only one way. Gshare branch predictor is employed to predict the instruction flow and determine the way to fetch the instruction. When the branch prediction is untaken, next instruction in a sequential order can be fetched from the instruction cache by accessing only one way. According to our simulations with SPEC2006 benchmarks, the proposed technique requires negligible hardware overhead and shows 20% energy reduction on average in 4-way L1 instruction cache.

• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1406-1416
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• 2017

In complex and large-scale industries, properly designed fault detection and identification (FDI) systems considerably improve safety, reliability and availability of target processes. In thermal power plants (TPPs), generating units operate under very dangerous conditions; system failures can cause severe loss of life and property. In this paper, we propose a bagged auto-associative kernel regression (AAKR)-based FDI approach for steam boilers in TPPs. AAKR estimates new query vectors by online local modeling, and is suitable for TPPs operating under various load levels. By combining the bagging method, more stable and reliable estimations can be achieved, since the effects of random fluctuations decrease because of ensemble averaging. To validate performance, the proposed method and comparison methods (i.e., a clustering-based method and principal component analysis) are applied to failure data due to water wall tube leakage gathered from a 250 MW coal-fired TPP. Experimental results show that the proposed method fulfills reasonable false alarm rates and, at the same time, achieves better fault detection performance than the comparison methods. After performing fault detection, contribution analysis is carried out to identify fault variables; this helps operators to confirm the types of faults and efficiently take preventive actions.

• Journal of Fashion Business
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• v.22 no.2
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• pp.61-73
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• 2018

Power is the driving force of society, and the generation of power is inevitable. as long as society is rganized hierarchically. According to Michael Foucault's discourse modern power operates as a mechanism of 'panopticon', a system that monitors the 'body' of man through discipline. Moreover. fashion as acts as a symbol of beauty that continues to co-exist with power for the purpose of exposing status and authority, and for displaying the trends within a culture. So, it is necessary to study fashion design according to the changing power structure that exists in society. The aim of this study is to suggest types of creative fashion design process by visualizing the Foucault's power discourse through the image associative action. The four types of creative fashion design that have been drawn by visualizing Foucault's power discourse are as follow: disciplinary power, imprisonment power and knowledge power. The first type of fashion design method is to emphasize the shoulder by using shoulder pads, strings, tabs, and incisions in the clothing. The second method is to expose the body by using see-through material and manipulating its composition to expose the body. Third method is to borrowing elements of underwear. Fourth method is to utilize patterns that represent power, such as weapons, bones, blood, muscles, skulls, and various human imagesin the clothing. Through this study we expect to utilize creative fashion design to visualize concepts of the humanities, such as philosophical discourse.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• Journal of Power System Engineering
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• v.20 no.2
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• pp.66-72
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• 2016

As a method to improve the equipment reliability, early warning researches that can be detected fault symptom of an equipment at an early stage are being performed out among developed countries. In this paper, when abnormal signal is input to actual normal signal of a pump, early detection studies on pump's fault symptom were carried out with auto-associative kernel regression as an advanced pattern recognition algorithm. From analysis, correlations among power of motor driving pump, discharge flow of pump, power output of pump, and discharge pressure of pump are exited. When the abnormal signal is input to one of those normal signals, the other expected values are changed due to the influence of the abnormal signal. Therefore, the fault symptom of pump through the early-warning index is able to detect at an early stage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.453-461
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• 2010

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of embedded RISC core and a clock-gating algorithm using ODC (Observability Don't Care) operation to improve the power consumption of the core. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC core applied the proposed architecture is improved about 29% and dynamic power of the core using Chartered $0.18{\mu}m$ technology library is reduced by 16%.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.