• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2495-2502
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• 2012

This paper presents a new structure of phase looked loop (PLL) for replacing a process sensitive resistor in loop filter with an additional charge pump (CP). The additional charge pump works as a resistor in a loop filter. The output of two charge pumps changes same direction according to process variation. The simulation results according to process conditions(SS/TT/FF) demonstrate that the proposed PLL works properly with process variations. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by simulation with HSPICE.

• International Journal of Air-Conditioning and Refrigeration
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• v.11 no.4
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• pp.159-169
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• 2003

Five two-phase closed loop thermosyphons (TLTs) specially designed and constructed for the present study are one small scale loop, two medium scale loops (MSLI and MSLII) and two large scale loops (LSLI and LSLII). Two simulation models based on thermal resistance network, lumped and sectorial, are presented. In the Lumped model, the evaporator section is dealt as one lumped boiling section. Whereas, in the Sectorial model, all possible phenomena which would occur in the evaporator section due to the two-phase boiling process are considered in detail. Flow regimes, the flow transitions between flow regimes and other two-phase parameters involved in two-phase flows are carefully analyzed. In the present study, the results of two different simulation models are compared with experimental results. The comparisons showed that the simulation results by the Lumped model and by the Sectorial model did not show any partiality for the model used for the simulation. The simulation results according to the correlations show the various results in the large different range.

• Journal of the Korea Society for Simulation
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• v.6 no.2
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• pp.45-57
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• 1997

MAC (media access control) bridge is used to interconnect separate LANs and to relay frames between the BLANs (bridged LANs). Bridge architecture consists of MAC entity, MAC relay entity and bridge protocol entity protocol entity and performs learning, filtering and forwarding functions using filtering database. In this paper, we simulate these functions of bridge and the STP (spanning tree protocol). The STP derives an active topology from an arbitrarily connected BLAN. Our simulation model assumes a BLAN consisted of three bridge forming a closed loop. In order to remove the loop, each bridge process exchanges configruation BPDU (bridge protocol data unit0 with other bridge processes connected to the bridge itself. To simulate the communication between bridges, we implement the IPC (inter-process communication) server using message queues. Our simulation results show that the assumed BLAN contains no closed loop and then there is no alternative route and no unnecessary traffic.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.05a
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• pp.449-452
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• 2009

Optimized controller design for converters are very important because control-loop characteristics of converters determine the dynamic performances of converters. In addition, verification process of the control-loop characteristics by simulation and measurement with real hardware is sure to be performed after all parameters for controller and main power-stage are fixed. In this paper, general process for designing outer-loop controller of paralleling step-down converter is described. Simulation results are also contained for verifying validity of controller design results. Finally, voltage control-loop measurement method is explained and results are compared with simulation outputs.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.52-59
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• 1998

New types of PFD (phase-frequency detector) are proposed with reset time and propagation delay reduced. The perfomrance of our proposed PFDs are confirmed by SPICE simulation with 0.8.mu.m CMOS process parameter. As a result of simulation, the reset time of PFDs are 0.32 nsec and 0.030 nsec in capture-process. The proposed PFDs can be used in hihg-speed phase-licked loop (PLL).

• Journal of Korea Technical Association of The Pulp and Paper Industry
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• v.35 no.3
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• pp.1-12
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• 2003

The complexity of the papermaking system accelerates interactions between a large number of variables involved. The process operation, therefore, is subject to frequent perturbations by disturbance. Dynamic modelling is a useful tool for characterizing the transient behavior and selecting the best control strategies to reject disturbances. In this study we developed a dynamic simulation model of a fine paper production process, which consists of stock preparation, wire sections, white water circulations, and broke system. It focused on dynamic simulation in its role for developing control strategies and studying control loop dynamics related to filler loading for ash control. The results emphasized the importance of filler-loading position and length of control loop for rapid ash control and process stabilization.

• Korean Journal of Chemical Engineering
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• v.35 no.11
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• pp.2150-2156
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• 2018

We suggest a systematic method for obtaining the optimal compression ratio in the multi-stage closed-loop compression process of carbon dioxide. Instead of adopting the compression ratio of 3 to 4 by convention, we propose a novel approach based on mathematical analysis and simulation. The mathematical analysis prescribes that the geometric mean is a better initial value than the existing empirical value in identifying the optimal compression ratio. In addition, the optimization problem considers the initial installation cost as well as the energy required for the operation. We find that it is best to use the fifth stage in the general closed-loop type carbon dioxide multi-stage compression process.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.275-278
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• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.277-280
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• 2001

The proposed clock generator lowers the operating frequency in a system core though it keeps data bandwidth high because it has a multiphase clocking architecture. Moreover. it has a dual loop which is comprised of an inner analog phase generation loop and outer digital phase control loop. It has both advantages of DLL's wide operating range and DLL's low jitter The proposed design has been demonstrated in terms of the concept and Hspice simulation. All circuits were designed using a 0.25${\mu}{\textrm}{m}$ CMOS process and simulated with 2.5 V power supply.

• Journal of Korea Technical Association of The Pulp and Paper Industry
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• v.35 no.5
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• pp.46-52
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• 2003

In this work we developed the closed-loop model of a paper machine during grade change with the intention to provide a reliable dynamic model to be used in the model-based grade change control scheme. During the grade change, chemical and physical characteristics of paper process change with time. It is very difficult to represent these characteristics on-line by using physical process models. In this work, the wet circulation part and the drying section were considered as a single process and closed-loop identification technique was used to develop the grade change model. Comparison of the results of numerical simulations with mill operation data demonstrates the effectiveness of the model identified.