• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.71-80
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• 2004

This paper describes embedded processor architecture design which is applicable to multimedia in mobile platform The main description is based on basic processor architecture and consideration about energy efficiency when used in mobile platform To design processor data path architecture (pipeline, branch prediction, multiple issue superscalar, function unit number) which is optimal to multimedia application and cache hierarchy and its structure, we have nut the simulation with variant architecture using MPEG4 test bench as multimedia application. We analyzed energy efficiency of architecture to check if it is applicable to mobile platform and decide basic processor architecture based on analysis result. The suggested basic processor architecture not only can be applied to mobile platform but also can be applied to basic processor architecture of configurable processor which is designed through automatic design environment.

• Journal of IKEEE
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• v.18 no.3
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• pp.392-397
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• 2014

In this paper, we propose a memory operation system architecture for memory latency penalty reduction in SIMT architecture based stream processor. The proposed architecture applied non-blocking cache architecture to reduce cache miss penalty generated by blocking cache architecture. We verified that the proposed memory operation architecture improve the performance of the stream processor by comparing processing performances of various algorithms. We measured the performance improvement rate that was improved in accordance with the ratio of memory instruction in each algorithm. As a result, we confirmed that the performance of stream processor improves up to minimum 8.2% and maximum 46.5%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.10-21
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• 1997

In this paper, we propose multiple instruction issuable multi-streaming as a processor architecture for 3D graphics processor. Multistreaming can eliminate inteferences within concurrently executing instructions inthe pipelined processor to allow enough parallelism for parallel processing. Through cycle level simulation study, we show that the proposed architecture outperforms a conventional RISC processor, MIPS R3000 by three times with reasonable resource overheads. Multiple instruction issuable multistreaming processor will be a bood architecture for instruction processor when a large number of threads are guaranteed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.10
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• pp.1502-1507
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• 2012

In order to overcome the hardware complexity and power consumption problems, recently the multi-core architecture has been prevalent. For hardware simplicity, usually RISC processor is adopted as the unit core processor. However, if the performance of unit core processor is enhanced, the overall performance of the multi-core processor architecture can be further increased. In this paper, out-of-order superscalar processor is utilized for the multi-core processor architecture. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the out-of-order superscalar cores between 2 and 16 extensively. As a result, the 16-core out-of-order superscalar processor for the window size of 16 resulted in 17.4 times speed up over the single-core out-of-order superscalar processor, and 50 times speed up over the single core RISC processor. When compared for the same number of cores on the average, the multi-core out-of-order superscalar processor performance achieved 3.2 times speed up over the multi-core RISC processor and 1.6 times speed up over the multi-core in-order superscalar processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.664-665
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• 2013

This paper present a method of constructing the multimedia processor architecture. The proposed multimedia processor architecture be able to handle each text, sound, and video in one chip. Also it have interactive function that is a characteristics of multimedia. Specially, the proposed multimedia processor be able to addressing nodes in memory map without software, and it is completely reconfigurable depend on data. Also it as able to process time and space common that have synchronous/asynchronous and it is able to protect continuous and dynamic media bus collision, and local and overall common memory structure. The proposed multimedia processor architecture apply to virtual reality and mixed reality.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.417-420
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• 1999

This paper present the architecture and design of FFT processor for the OFDM modulation. The OFDM modulation have a merit that use frequecncy efficiently and robust ISI. It needs FFR to have fast and large number of points. Moreover, this FFT design has pipeline architecture. R2$^2$SDF architecture for FFT processor has more advantage others. Therefore this paper present FFT processor used R2$^2$SDF architecture.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1225-1240
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• 1999

This paper proposes PASC(PArtitioned SCHeduler) processor architecture that equips with a number of functional unit and an individual scheduler paris. Every scheduler of the PASC processor can determine whether a unit instruction can be issued to the associated functional unit or it is to be waited until next cycle caused by a resource collision or data dependencies. In the PASC processor, only the functional unit with a resource collision or data dependencies waits by executing a NOP(No OPeration) instruction and the other functional units execute their own instructions. Therefore we can expect the code compaction effect on the PASC processor. Thus, the last instruction of a loop at certain iteration and the very first instruction of the loop at the next iteration can be scheduled simultaneously if the two instructions do not incur any resource collision or data dependencies. Therefore, we can expect that such two instructions without any resource collision and data dependencies are packed into the same very long instruction word and thus, the two instructions are executed concurrently at run time. As a result, we can shorten execution cycles of a loop comparing to the execution of the loop on a traditional VLIW or SVLIW processor architecture. Simulation result also promises faster execution of loops on a PASC processor architecture than those on a VLIW and SVLIW processor architecture.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.1081-1087
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• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1128-1133
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• 2008

Context-aware computing has been attracting the attention as an approach to alleviating the inconvenience in human-computer interactions. This paper proposes a context-aware system architecture to be implemented on an UoC (Ubiquitous system on Chip). A new proposed technology of CRS (Context Recognition Switch) and DOS (Dynamic and Optimal Standard) based on Context-awareness system architecture with pre-processor, HPSP(High Performance Signal Processor) in this paper. And proposed a new algorithm using in network topology processor shows for Ubiquitous Computing System. implementing in UoC (Ubiquitous System on Chip) base on the IEEE 802.15.4 WPAN (Wireless Personal Area Network) standard. Also, This context-aware based UoC architecture has been developed to apply to mobile intelligent robots which would support human in a context-aware manner.