• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.220-223
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• 2002

The digital logic systems(DLS) is classified into digital combinational logic systems(CDLS) and digital sequential logic systems(SDLS). This paper presents a method of constructing the digital sequential logic systems without feedback. Firstly we assign all elements in Finite Fields to P-valued digit codes using mathematical properties of Finine Fields. Also, we discuss the operarional properties of the building block T-gate that is used to realizing digital sequential logic systems over Finite Fields. Then we realize the digital sequential logic systems without feedback. This digital sequential logic systems without feedback is constructed ny following steps. Firstly, we assign the states in the state-transition diagram to state P-valued digit dodo, then we obtain the state function and predecessor table that is explaining the relationship between present state and previous states. Next, we obtained the next-state function and predecessor table. Finally, we realize the circuit using T-gate and decoder.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.6
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• pp.1441-1446
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• 2010

This paper presents a method of constructing the divider using sequential logic systems over finite fields(or galois fields). The proposed the sequential logic systems is constructed by as following. First of all, we obtain the linear characteristics between present state and next state based on mathematical properties of finite fields and sequential logic systems. Next, we realize the sequential logic systems over finite fields using above linear characteristics and characteristic polynomial which is expressed using by matrix. Also, we apply to implement divider using the proposed sequential logic systems over finite fields.

• Journal of information and communication convergence engineering
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• v.8 no.4
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• pp.421-426
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• 2010

This paper presents a method of design the counter using sequential system based on synchronous techniques. For the design the counter, first of all, we derive switching algebras and their operations. Also, we obtain the next-state functions, flip-flop excitations and their input functions from the flip-flop. Then, we propose the algorithm which is a method of implementation of the synchronous sequential digital logic circuits. Finally, we apply proposed the sequential logic based on synchronous techniques to counter.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.3
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• pp.254-261
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• 2005

Time-optimal performances are analyzed in the sense of inner loop. A varying-time sharing thrusting logic is suggested as a new sequential paired thrusting logic for fast maneuvers of satellites with coupled thruster configuration. Its time-optimal maneuvering performance is compared with two conventional thrusting logics: separate thrusting logic and constant-time sharing sequential paired thrusting logic. It is found that the newly suggested varying-time sharing thrusting logic can be easily implemented by adjusting the conventional constant-time logic with its thrust on-time, while it can reduce the maneuvering time enormously as much as the separate thrusting logic. The performance of the logic is simulated on the agile maneuvering spacecraft model KOMPSAT-II.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of Ocean Engineering and Technology
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• v.13 no.3B
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• pp.106-115
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• 1999

Modeling a discrete event system such as a sequential control system is difficult compared with a continuous system. Petri nets have been introduced as an analyzing and design tool for the discrete systems. One of the problems in its applications is that the model can not be analyzed easily in the case of large scale or complicated systems because of increase of the number of components of the system. To overcome this problem, some methods for dividing or reducing Petri nets have been suggested. In this paper, an approach for a hierarchical expression of Petri nets based on Sequential Function Chart(SFC) is proposed. A measuring tank system will be described as a typical kind of discrete systems. The system is modeled by sub Petri nets based on SFC in order to analyze and visualize efficiently about the dynamic behaviors of the system. Some numerical simulations using state equations are performed to prove the validity of the proposed method.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.564-571
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• 1996

The logic synthesis systems for table look up(TLU) type field programmable e gate arrays(FPGAs) have so farstudied mostly the combinational logic problem m. This paper presents for mapping a sequential circuit onto a popular table look up architecture, theXilinx 3090 architecture. In thefirst for solving this problem, combinational and sequential elements which have 6 or7 input combinational and sequential elements which haveless thanor equal to 5 inputs. We heavily use the combinational synthesis techniques tosolve the sequential synthesis problem. Our syntheisis approach is very simple, but its results are reasonable. We compare seveal benchmark Examples with sis-pga(map_together and map_separate) synthesis system and the experimental results show that our synthesis system is 17% betterthan sis-pga sequential synthesis system for TLU PGAs.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2001.05a
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• pp.26-31
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• 2001

Petri nets(PN) have been introduced as a poweful analyzing and design tool for the discrete systems such as sequential control systems. However, one of the important problems in its applications is that the model can not be analyzed easily when we deal with large scale systems because of increase of the number of components of the systems. To overcome this problem, some methods for dividing or reducing of PN have been suggested. In this paper, an approach for hierarchical expression of PN based on Sequential Function Chart(SFC) and Bottom Up oriented Mehodology(BUM) is proposed. Especially, some definition and rules are defined in order to divide and compose sub PN. A measuring tank system will be described as a typical kind of discrete systems and modeled by some sub PN based on the SFC and BUM by the proposed method in this paper.

• Journal of Korean Society for Quality Management
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• v.11 no.2
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• pp.2-9
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• 1983

As will be seen, this paper is tries that the research on the mathematical structure of Markov process and Markovian sequential decision process (the policy improvement iteration method,) moreover, that it analyze the logic and the characteristic of behavior of mathematical model of Markov process. Therefore firstly, it classify, on research of mathematical structure of Markov process, the forward equation and backward equation of Chapman-kolmogorov equation and of kolmogorov differential equation, and then have survey on logic of equation systems or on the question of uniqueness and existence of solution of the equation. Secondly, it classify, at the Markovian sequential decision process, the case of discrete time parameter and the continuous time parameter, and then it explore the logic system of characteristic of the behavior, the value determination operation and the policy improvement routine.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.56-63
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• 1984

This paper proposes a programmed logic realization of sequential logic system with parallel sequences which is described by a GRAFCET. For this purpose, an algorithm is proposed, which decomposes the GRAFCET with parallel sequence into a set of state graph without changing the physical meaning, which is applied to all kinds of GRAFCET, and which divides the system into sub-systems and vice versa. A systematic implementation by microprogrammed logic using ROM is proposed, which expands the number of selection sequence.