• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.328-332
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• 2006

Efficient finite field operation in the elliptic curve (EC) public key cryptography algorithm, which attracts much of latest issues in the applications in information security, is very important. Traditional serial finite multipliers root from Mastrovito's serial multiplication architecture. In this paper, we adopt the polynomial basis and propose a new finite field multiplier, inducing numerical expressions which can be applied to exhibit 3 times as much performance as the Mastrovito's. We described the proposed multiplier with HDL to verify and evaluate as a proper hardware IP. HDL-implemented serial GF (Galois field) multiplier showed 3 times as fast speed as the traditional serial multiplier's adding only partial-sum block in the hardware. So far, there have been grossly 3 types of studies on GF($2^m$) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5401-5421
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• 2016

Both low-density parity-check (LDPC) codes and the multiple access technique of spatially coupling data transmission (SCDT) can be expressed in bipartite graphs. To improve the performance of iterative demodulation and decoding for SCDT, a novel joint sparse graph (JSG) with SCDT and LDPC codes is constructed. Based on the JSG, an approach for iterative joint demodulation and decoding by belief propagation (BP) is presented as an exploration of the flooding schedule, and based on BP, density evolution equations are derived to analyze the performance of the iterative receiver. To accelerate the convergence speed and reduce the complexity of joint demodulation and decoding, a novel serial schedule is proposed. Numerical results show that the joint demodulation and decoding for SCDT based on JSG can significantly improve the system's performance, while roughly half of the iterations can be saved by using the proposed serial schedule.

• Journal of English Language & Literature
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• v.64 no.4
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• pp.601-616
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• 2018

This article explores the ways Charles Dickens's roles as novelist and journal editor overlapped and influenced one another in the serial publication of A Tale of Two Cities (1859) and complicates recent historicist readings, which situate the novel in relation to the Indian Mutiny (1857-59), by calling attention to a double imperial logic used to construct British subjectivity not only against forms of Eastern Otherness but, moreover, against forms of Southern Otherness associated with the European South, especially Italy. Analyzing Dickens's historical representation of the French Revolution in relation to its contemporary international political context, this essay examines how the novel's serial publication draws upon political discourse from contemporary articles on the Second Italian War of Independence (1859-61) appearing concurrently in Dickens's journal, All the Year Round. Orientalism circulates simultaneously in the novel as a distant and exotic as well as a provincial and parochial representation of racial and cultural Otherness.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.776-783
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• 2009

Current-cut circuit is an effective method to obtain low power consumption in wireless communication systems as high speed OFDM. For the operation of current-mode FFT LSI with analog signal processing essentially requires current-mode serial-to-parallel/parallel-to-serial converter with multi input and output structure. However, the Hold-mode operation of current-mode serial-to-parallel/parallel-to-serial converter has unnecessary power consumption. We propose a novel current-mode serial-to-parallel/parallel-to-serial converter with current-cut circuit and full chip simulation results agree with experimental data of low power consumption. The proposed current-mode serial-to-parallel/parallel-to-serial converter promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.525-529
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• 2004

A novel translational 3-dof parallel mechanism is proposed and analyzed. The mechanism consists of three RRPS serial subchains and an additional passive 3-dof type serial subchain. Three RRPS serial subchains alone may form a structure of the 6-DOF Stewart Platform mechanism. However, in the proposed mechanism, an additional passive serial subchain acts as constraints to restrict the output motion of the mechanism in 3-DOF translational space. The closed form position solutions of the proposed mechanism and its first-order kinematic model are derived. Then its workspace size and kinematic characteristics are examined via kinematic isotropic index.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.520-524
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• 2004

In this work, a novel spherical 3-dof parallel mechanism is proposed and analyzed. The mechanism consists of three RRPS serial subchains and an additional passive 3-dof type serial subchain. Three RRPS serial subchains alone may form a structure of 6-DOF Stewart Platform mechanism. However, in the proposed mechanism, an additional passive serial subchain acts as constraints to restrict the output motion of the mechanism within 3-DOF spherical space. The closed form solutions of position analysis of the proposed mechanism and its first-order kinematic model are derived. Then its workspace size and kinematic characteristics are examined via kinematic isotropic index.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1188-1193
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• 2004

So far, there have been grossly 3 types of studies on GF(2m) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. Serial multiplication method was first suggested by Mastrovito (1), to be known as the basic CF(2m) multiplication architecture, and this method was adopted in the array multiplier (2), consuming m times as much resource in parallel to extract m times of speed. In 1999, Paar studied further to get the benefit of both architecture, presenting the hybrid multiplication architecture (3). However, the hybrid architecture has defect that only complex ordo. of finite field should be used. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software. The implemented GF(2m) multiplier shows t times as fast as the traditional one, if we modularized the numerical expression by t number of parts.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.6
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• pp.188-198
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• 1994

The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

• Journal of the Korean Society of Industry Convergence
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• v.17 no.3
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• pp.84-92
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• 2014

In this paper, a novel 5-axis hybrid-kinematic machine tool is introduced and the research results on accuracy improvement of the prototype machine tool are presented. The 5-axis hybrid machine tool is made up of a 3-DOF parallel manipulator and a 2-DOF serial one connected in series. The machine tool maintains high ratio of stiffness to mass due to the parallel structure and high orientation capability due to the serial-type wrist. In order to acquire high accuracy, the methodology of measuring the output shafts by additional sensors instead of using encoder outputs at the motor shafts is proposed. In the kinematic view point, the hybrid manipulator reduces to a serial one, if the passive joints in the U-P serial chain at the center of the parallel manipulator are directly measured by additional sensors. Using the method of successive screw displacements, the kinematic error model is derived. Since a ball-bar is less expensive than a full position measurement device and sufficiently accurate for calibration, the kinematic calibration method of using a ball-bar is presented. The effectiveness of the calibration method has been verified through the simulations. Finally, the calibration experiment shows that the position accuracy of the prototype machine tool has been improved from 153 to $86{\mu}m$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.39-45
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• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.