• Title/Summary/Keyword: short channel effects

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Control of Short-Channel Effects in Nano DG MOSFET Using Gaussian-Channel Doping Profile

  • Charmi, Morteza
    • Transactions on Electrical and Electronic Materials
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    • v.17 no.5
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    • pp.270-274
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    • 2016
  • This article investigates the use of the Gaussian-channel doping profile for the control of the short-channel effects in the double-gate MOSFET whereby a two-dimensional (2D) quantum simulation was used. The simulations were completed through a self-consistent solving of the 2D Poisson equation and the Schrodinger equation within the non-equilibrium Green’s function (NEGF) formalism. The impacts of the p-type-channel Gaussian-doping profile parameters such as the peak doping concentration and the straggle parameter were studied in terms of the drain current, on-current, off-current, sub-threshold swing (SS), and drain-induced barrier lowering (DIBL). The simulation results show that the short-channel effects were improved in correspondence with incremental changes of the straggle parameter and the peak doping concentration.

Impact of Fin Aspect Ratio on Short-Channel Control and Drivability of Multiple-Gate SOI MOSFET's

  • Omura, Yasuhisa;Konishi, Hideki;Yoshimoto, Kazuhisa
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.4
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    • pp.302-310
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    • 2008
  • This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

Analysis of Short Channel Effects Using Analytical Transport Model For Double Gate MOSFET

  • Jung, Hak-Kee
    • Journal of information and communication convergence engineering
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    • v.5 no.1
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    • pp.45-49
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    • 2007
  • The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

Optimizing Effective Channel Length to Minimize Short Channel Effects in Sub-50 nm Single/Double Gate SOI MOSFETs

  • Sharma, Sudhansh;Kumar, Pawan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.2
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    • pp.170-177
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    • 2008
  • In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

The Characterizing Analysis of a Buried-Channel MOSFET based on the 3-D Numerical Simulation

  • Kim, Man-Ho;Kim, Jong-Soo
    • Journal of Electrical Engineering and Technology
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    • v.2 no.2
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    • pp.267-273
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    • 2007
  • A depletion-mode MOSFET has been analyzed to evaluate its electrical behavior using a novel 3-D numerical simulation package. The characterizing analysis of the BC MOSFET was performed through short-channel narrow-channel and small-geometry effects that are investigated, in detail, in terms of the threshold voltage. The DIBL effect becomes significant for a short-channel device with a channel length of $<\;3({\mu}m)$. For narrow-channel devices the variation of the threshold voltage was sharp for $<4({\mu}m)$ due to the strong narrow-channel effect. In the case of small-geometry devices, the shift of the threshold voltage was less sensitive due to the combination of the DIBL and substrate bias effects, as compared with that observed from the short-channel and narrow-channel devices. The characterizing analysis of the narrow-channel and small-geometry devices, especially with channel width of $<\;4({\mu}m)$ and channel area of $<\;4{\times}4({\mu}m^2)$ respectively, can be accurately performed only from a 3-D numerical simulation due to their sharp variations in threshold voltages.

Device Optimization for Suppression of Short-Channel Effects in Bulk FinFET with Vacuum Gate Spacer (진공 게이트 스페이서를 지니는 Bulk FinFET의 단채널효과 억제를 위한 소자구조 최적화 연구)

  • Yeon, Ji-Yeong;Lee, Khwang-Sun;Yoon, Sung-Su;Yeon, Ju-Won;Bae, Hagyoul;Park, Jun-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.35 no.6
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    • pp.576-580
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    • 2022
  • Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity

  • Sharma, Sudhansh;Kumar, Pawan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.3
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    • pp.136-147
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    • 2009
  • In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

Supperession of Short Channel Effects in 0.1$\mu\textrm{m}$ nMOSFETs with ISRC Structure (짧은 채널 효과의 억제를 위한 ISRC (Inverted-Sidewall Recessed-Channel)구조를 갖는 0.1$\mu\textrm{m}$ nMOSFET의 특성)

  • 류정호;박병국;전국진;이종덕
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.34D no.8
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    • pp.35-40
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    • 1997
  • To suppress the short channel effects in nMOSFET with 0.1.mu.m channel length, we have fabricated and characterized the ISRC n MOSFET with several process condition. When the recess oxide thickness is 100nm and the channel dose for threshold voltge adjustment is 6*10$^{12}$ /c $m^{-2}$ , B $F_{2}$$^{+}$, the maximum transconductance at $V_{DS}$ =2.0V is 455mS/mm and the BIDL is kept within 67mV. By comparing the ISRC n MOSFET with the conventioanl SHDD (shallowly heavily dopped drain) nMOSFET, we verify the suppression of short channel effects ISRC structure.e.

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A Study on Short Channel Effects of n Channel Polycrystalline Silicon Thin Film Transistor Fabricated at High Temperature (고온에서 제작된 n채널 다결정 실리콘 박막 트랜지스터의 단채널 효과 연구)

  • Lee, Jin-Min
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.24 no.5
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    • pp.359-363
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    • 2011
  • To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.

Drain induced barrier lowering and impact ionization effects in short channel polysilicon TFTs

  • Fortunato, G.;Valletta, A.;Gaucci, P.;Mariucci, L.;Cuscuna, M.;Maiolo, L.;Pecora, A.
    • 한국정보디스플레이학회:학술대회논문집
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    • 2008.10a
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    • pp.907-910
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    • 2008
  • The effect of channel length reduction on the electrical characteristics of self-aligned polysilicon TFTs has been investigated by combining experimental characteristics and 2-D numerical simulations. The role of drain induced barrier lowering and floating body effects has been carefully analized using numerical simulations.

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