• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.970-973
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• 2003

Abstract An idea to redce the direct-path short circuit current of the CMOS digital integrated circuit is present. The sample circuit model of the CMOS digital circuit is the CMOS current-control digital output driver circuit, which are also suitable for the low voltage supply integrated circuits as the simple digital inverter, are present in this title. The circuit consists of active MOS load as the current control source, which construct from the saturated n-channel and p-channel MOSFET and the general CMOS inverter circuits. The saturated MOSFET bias can control the output current and the frequency response of the circuit. The experimental results show that lower short circuit current control can make the lower frequency response of the circuit.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.1-9
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• 1998

In the circuit model that outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical pathe may not improve the performance. Since the clock period is etermined by delays of both long and short paths in combinational circuits, the performance (clock period) can be optimized by decreasing the delay of the longest path, or increasing the delay of the shortest path. In order to achieve the desired clock period of a circuit, gates lying in sensitizable long and short paths can be selected for resizing. However, the gate selection in path sensitization approach is a difficult problem due to the fact that resizing a gate in shortest path may change the longest sensitizable path and viceversa. For feasible settings of the clock period, new algorithms and corresponding gate selection methods for resizing are proposed in this paper. Our new gate selection methods prevent the delay of the longest path from increasing while resizing a gate in the shortest path and prevent the delay of the shortest path from decreasing while resizing a gate in the longest sensitizable path. As a result, each resizing step is guaranteed not to increase the clock period. Our algorithmsare teted on ISCAS85 benchmark circuits and experimental results show that the clock period can beoptimized efficiently with out gate selection methods.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.140-145
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• 2002

A new CMOS buffer removing short-circuit power consumption is proposed. The gate-driving signal of the pull-up(pull-down) transistor at the output is controlled by delayed internal signal to get tri-state output momentarily by shunting off the path of the short-circuit current. The SPICE simulation results verified the operation of the proposed buffer and showed the enhancement of the power-delay product at 3.3V supply voltage about 42% comparing to the conventional tapered CMOS buffer(1).

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2278-2288
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• 2017

Multilevel converter topologies are widely used in many applications. The cascaded H-bridge multilevel inverter (CHBMI), which is one of many multilevel converter topologies, has been introduced as a useful topology in high and medium power. However, it has a drawback to require a lot of switches. Therefore, the reliability of CHBMI is important factor for analyzing the performance. This paper presents a simple switch fault diagnosis method for single-phase CHBMI. There are two types of switch faults: open-fault and short-fault. In the open-fault, the body diode of faulty switch provides a freewheeling current path. However, when the short-fault occurs, the distortion of output current is different from that of the open-fault because it has an unavailable freewheeling current flow path due to a disconnection of fuse. The fault diagnosis method is based on the zero current time analysis according to zero-voltage switching states. Using the proposed method, it is possible to detect the location of faulty switch accurately. The PSIM simulation and experimental results show the effectiveness of proposed switch fault diagnosis method.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1924-1937
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• 1996

In this paper, we propose a ESP(Extended Scan Path) architecture for multi- board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan paths either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using, he proposed ESP architecture, we observed to the test time is short compared with the single scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS '85 bench mark circuit, we showed that the architecture has improved results.

• Current Optics and Photonics
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• v.7 no.1
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• pp.38-46
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• 2023

Optical Fourier-domain reflectometry (OFDR) sensors have been widely used to measure distances with high resolution and speed in a noncontact state. In the electroplating process of a printed circuit board, it is critically important to monitor the copper-plating thickness, as small deviations can lead to defects, such as an open or short circuit. In this paper we employ a phase-based OFDR sensor for in situ relative distance sensing of a sample with nanometer-scale resolution, during electroplating. We also develop an optical-path difference (OPD)-regulated sensing probe that can maintain a preset distance from the sample. This function can markedly facilitate practical measurements in two aspects: Optimal distance setting for high signal-to-noise ratio OFDR sensing, and protection of a fragile probe tip via vertical evasion movement. In a sample with a centimeter-scale structure, a conventional OFDR sensor will probably either bump into the sample or practically out of the detection range of the sensing probe. To address this limitation, a novel OPD-regulated OFDR system is designed by combining the OFDR sensing probe and linear piezo motors with feedback-loop control. By using multiple OFDR sensors, it is possible to effectively monitor copper-plating thickness in situ and uniformize it at various positions.

• Journal of IKEEE
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• v.20 no.4
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• pp.361-366
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• 2016

This paper presents the ESD protection circuit with improved electrical characteristic and area efficiency. The proposed ESD protection circuit has higher holding voltage and lower trigger voltage characteristics than the 3-Stacking LVTSCR. In addition, it has only two stages and has improved Ron characteristics due to short discharge path of ESD current. We analyzed the electrical characteristics of the proposed ESD protection circuit by TCAD simulator. The proposed ESD protection circuit has a small area of about 35% compared with 3-Stacking LVTSCR, The proposed circuit is designed to have improved latch-up immunity by setting the effective base length of two NPN parasitic bipolar transistors as a variable.

• Bulletin of the Korean Chemical Society
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• v.34 no.9
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• pp.2765-2768
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• 2013

The effect of $TiO_2$ nanorods (TNR) and nanoparticles (TNP) composite photoelectrodes and the role of TNR to enhance the energy conversion efficiency in dye-sensitized solar cells (DSSCs) was investigated. The 5% TNR content into the TNP photoelectrode significantly increased the short-circuit current density ($J_{sc}$) and the open-circuit potential ($V_{oc}$) with the overall energy conversion efficiency enhancement of 13.6% compared to the pure TNP photoelectrode. From the photochemical and impedemetric analysis, the increased $J_{sc}$ and $V_{oc}$ for the 5% TNR/TNP composite photoelectrode was attributed to the scattering effect of TNR, reduced electron diffusion path and the suppression of charge recombination between the composite photoelectrode and electrolyte or dye.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.298-303
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• 2013

In this study, the W-interconnected dye-sensitized solar cell (DSSC) modules composed of a number of rectangular cells connected in series were investigated, where neighboring cells are processed in reverse. The DSSC modules, a module of dimension about 200 mm ${\times}$ 200 mm, were fabricated with different working electrode width ranging from 5 mm to 21 mm. The short-circuit current of the module increased as the working electrode width increased. Whereas, the decrease in the working electrode width resulted in the increase of the conversion energy efficiency, fill factor, and open-circuit voltage, which is explained by the fact that the possibility that electrons are recombined along their path on the transparent conductive oxide substrate decreases. The module with the conversion energy efficiency of 3.59% was obtained with the working electrode width of 5 mm.

• Journal of electromagnetic engineering and science
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• v.7 no.4
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• pp.147-153
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• 2007

This paper represents an analog predistortion linearizer for the high power amplifier with low memory effect. The high power amplifier is implemented using a 90-W peak envelope power(PEP) LDMOSFET at 2.14-GHz and an envelope short matching topology is applied at the active ports to minimize the memory effect. The analog predistortion circuit comprises the fundamental path and the cuber and quintic generating circuits, whose amplitudes and phases can be controlled independently. The predistortion circuit is tested for two-tone and wide-band code division multiple access(WCDMA) 4FA signals. For the WCDMA signal, the adjacent channel leakage ratios(ACLRs) at 5 MHz offset are improved by 12.4 dB at average output powers of 36 dBm and 42 dBm.