• Tribology and Lubricants
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• v.11 no.5
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• pp.20-25
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• 1995

Diamond films were prepared by a hot filament vapor deposition onto polycrystal silicon nitride substrates. Different kinds of silicon nitride containing CaO and $Fe_{2}O_{3}$ were manufactured to investigate the impurity effect of substrate on the morphology of diamond films and their wear behaviors. Nucleation rates and morphologies of diamond films deposited on various kinds of silicon nitride were compared. The highest nucleation rate was observed in a substrate containing 1% of CaO. Wear tests were performed with a silicon nitride ball on the disk geometry to investigate the tribological behavior of diamond film against silicon nitride. This study demonstrated that different morphologies of diamond film due to substrate impurities produced different wear behavior against silicon nitride.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.393-396
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• 1999

A circuit model of silicon substrate coupling for CMOS RF-IC design is developed. Its characteristics are analyzed by using a simple RC mesh model in order to investigate substrate coupling. The coupling effects due to the substrate were characterized with substrate resistivity, oxide thickness, substrate thickness. and physical distance. Thereby the silicon substrate effects are analytically investigated and verified with simulation. The analysis and simulation of the model have excellent agreements with MEDICI(2D device simulator) simulation results.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.217-221
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• 2016

In this work, open and short stubs that were fabricated on the silicon substrate and for which the periodically arrayed grounded-strip structure (PAGS) was employed were studied along with their basic RF characteristics for an applicability regarding the RF-matching components. The PAGS-employing open and short stubs showed losses that are much lower than that of the conventional stub on the silicon substrate. Concretely, the Q values of the open and short stubs are 9 and 10.2, respectively, while the Q value of the conventional open stub is 2.5. With the use of the PAGS-employing open and short stubs, a highly miniaturized harmonic-rejection filter was also fabricated on the silicon substrate. The filter exhibited a comparatively sound harmonic-suppression characteristic at n × 13 GHz, and its size is 0.1 mm², which is only 7% of the size of the conventional filter on the silicon substrate.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.871-874
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• 1998

A new transmission line parameter extraction method of iC interconnects on silicon substrate is presented. To extract the acurate parameters, the silicon substrate effects were taken into account. Since the electromagnetic fields under the silicon substrate are propagated with slow wave mode, effective dielectric constant and different ground plane with the multi-layer dielectric structures were employed for inductance and capacitance matrix determination. Then accurate signal transients simulation were performed with HSPICE by using the parameters. It was shown that the simulation resutls has an excellent agreement with TDR/TDT measurements.

• Journal of Integrative Natural Science
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• v.6 no.3
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• pp.170-175
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• 2013

Silicon nanowires were detached and obtained from silicon nanowire arrays on silicon substrate using a ultrasono-method. Silicon nanowire arrays on silicon substrate were prepared with an electroless metal assisted etching of p-type silicon. The etching solution was an aqueous HF solution containing silver nitrate. SEM observation shows that well-aligned nanowire arrays perpendicular to the surface of the silicon substrate were produced. After sonication of silicon nanowire array, an individual silicon nanowire was confirmed by FESEM. Optical characteristics of SiNWs were measured by FT-IR spectroscopy. The surface of SiNWs are terminated with hydrogen.

• Journal of Powder Materials
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• v.24 no.3
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• pp.248-253
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• 2017

In this study, we investigate the effect of the diffusion barrier and substrate temperature on the length of carbon nanotubes. For synthesizing vertically aligned carbon nanotubes, thermal chemical vapor deposition is used and a substrate with a catalytic layer and a buffer layer is prepared using an e-beam evaporator. The length of the carbon nanotubes synthesized on the catalytic layer/diffusion barrier on the silicon substrate is longer than that without a diffusion barrier because the diffusion barrier prevents generation of silicon carbide from the diffusion of carbon atoms into the silicon substrate. The deposition temperature of the catalyst and alumina are varied from room temperature to $150^{\circ}C$, $200^{\circ}C$, and $250^{\circ}C$. On increasing the substrate temperature on depositing the buffer layer on the silicon substrate, shorter carbon nanotubes are obtained owing to the increased bonding force between the buffer layer and silicon substrate. The reason why different lengths of carbon nanotubes are obtained is that the higher bonding force between the buffer layer and the substrate layer prevents uniformity of catalytic islands for synthesizing carbon nanotubes.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.611-611
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• 2013

In this study, iron oxide nanoclusters layer (Nc) was prepared onto functionalized silicon substrate by wet method. The amine-terminated SAM fabricated on silicon substrate (APTMS/Si) was carried out by UV-treatment and immersed into the FeCl3/HCl aqueous solution. Then, Nc were immobilized onto oxidized SAM silicon substrate (SAMs/Si) through electrostatic interaction between cationic Nc and anionic SAMs/Si. This catalytic layer (Nc/SAMs/Si) was used to grow carbon nanotubes (CNTs). The characterization results clearly show that the well-graphitized CNTs were synthesized by using functionalized silicon substrate as a template having appropriate density of catalyst. These consequences show that SAM containing template is important to achieve the effective layer of catalyst to synthesize CNTs.

• Transactions on Electrical and Electronic Materials
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• v.17 no.2
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• pp.118-120
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• 2016

A coplanar waveguide employing periodic 3D coupling structures (CWP3DCS) was developed for application in miniaturized on-chip passive components on silicon radio frequency integrated circuits (RFIC). The CWP3DCS showed the shortest wavelength of all silicon-based transmission line structures that have been reported to date. Using CWP3DCS, a highly miniaturized impedance transformer was fabricated on silicon substrate, and the resulting device showed good RF performance in a broad band from 4.6 GHz to 28.6 GHz. The device as was 0.04 mm² in size, which is only 0.74% of the size of the conventional transformer on silicon substrate.

• Korean Journal of Crystallography
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• v.12 no.3
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• pp.166-170
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• 2001

Dopants implanted in silicon substrate affect the reaction between cobalt and silicon substrate. Phosphorous, unlike boron and arsenic, suppressing the reaction between cobalt and silicon induces CoSi formation during a low temperature thermal treatment instead of CoSi₂formation. The CoSi layer should move to the silicon substrate to fill the vacant volume that is generated in the silicon substrate due to the silicon out-diffusion into the cobalt/CoSi interface. The movement of CoSi at gate sidewall spacer region is suppressed by a cohesion between gate oxide and CoSi layers, resulting in a void formation at the gate sidewall spacer edge.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.781-790
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• 2001

The effects of silicon substrate thickness on the performance of thin film PZT IR detectors are theoretically and experimentally investigated. Theoretical analyses show that the pyroelectric current responsivity of a detector without a silicon substrate is about two orders higher than that of a detector with a 450${\mu}{\textrm}{m}$ thick silicon substrate. At a fixed chopping frequency of 100Hz, the pyroelectric current responsivity decreases exponentially with increasing silicon substrate thickness up to 50${\mu}{\textrm}{m}$, and above 50${\mu}{\textrm}{m}$ the decreasing rate become slow. The thinner the silicon substrate is, the less the thermal loss by conduction is , and thus the higher responsivity is resulted. To verify the theoretical analyses, micromachined PZT thin film IR detectors with different silicon substrate thicknesses are fabricated and characterized. The theoretical and experimental results show the similar tendencies for all silicon substrates with varying thickness.