• 한국진공학회지
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• 제7권1호
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• pp.29-34
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• 1998

PECVD방법으로 증착된 비정질 실리콘(a-Si)박막이 고상결정화되고 x-선 회절 (XRD)방법으로 조사되었다. a-Si박막들은 기판 온도 120-$380^{\circ}C$사이에서 Si(100)웨이퍼 위에 $SiH_4$가스 혹은 수소희석된 $SiH_4$가스로 증착되고, $600^{\circ}C$로 가열되어 결정화되었다. 고상화 되었을 때(111), (220), (311)XRD피크들이 나타났고 (111) 우선방위가 두드러졌다. 고상결정 화된 다결정 실리콘(poly-Si)박막들의 XRD피크의 세기는 기판온도가 낮아짐에 따라 증가되 었고, 수소희석은 고상화 효과를 감소시켰다. XRD로 측정된(111)결정립의 평균크기는 기판 온도가 낮아짐에 따라 약 10nm로 증가하였다. 기판온도가 낮아질수록 증착속도는 증가하였 으며, 결정의 크기는 증착속도와 밀접한 관계가 있었다. Si계의 구조적 무질서도가 클수록 고상화에 의한 결정립의 크기도 커지는 것으로 생각된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.42-45
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• 1992

The poly silicon thin films were prepared by solid phase crystallization at 600$^{\circ}C$ of amorphous silicon films deposited on Corning 7059 glass and (100) silicon wafer with thermally grown SiO$_2$substrate by plasma enhanced chemical vapor deposition with varying rf power, deposition temperature, total flow rate. Crystallization time, microstructure, absorption coefficients were investigated by RAMAN, XRD analysis and UV transmittance measurement. Crystallization time of amorphous silicon films was increased with increasing rf power, decreasing deposition temperature and decreasing total flow rate.

• 한국표면공학회지
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• 제47권1호
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• pp.20-24
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• 2014

Joule heat is generated by applying an electric filed to a conductive layer located beneath or above the amorphous silicon film, and is used to raise the temperature of the silicon film to crystallization temperature. An electric field was applied to an indium tin oxide (ITO) conductive layer to induce Joule heating in order to carry out the crystallization of amorphous silicon. Polycrystalline silicon was produced within the range of a millisecond. To investigate the kinetics of Joule-heating induced crystallization (JIC) solid phase crystallization was conducted using amorphous silicon films deposited by plasma enhanced chemical vapor deposition and using tube furnace in nitrogen ambient. Microscopic and macroscopic uniformity of crystallinity of JIC poly-Si was measured to have better uniformity compared to that of poly-Si produced by other methods such as metal induced crystallization and Excimer laser crystallization.

• 한국진공학회지
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• 제14권1호
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• pp.24-28
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• 2005

a-Si을 poly-Si으로 결정화하는 전형적인 방법으로는 고상결정화(Solid Phase Crystallization, SPC)가 있다［1-3］. 고상결정화는 균일한 공정특성과 생산비가 저렴하다는 장점이 있으나, 고상결정화 공정에서 높은 공정온도와 긴 공정 시간은 유리 기판의 손상으로 인해 적용되기 어렵다. 본 논문에서는 고상결정화의 저온공정과 짧은 공정시간을 위해 교번자장결정화(Alternating Magnetic Field Crystallization, AMFC) 시스템 내에서 결정화하는 동안 교번자장(Alternating Magnetic Field)을 적용하는 새로운 방법을 소개한다. 고상결정화의 경우, 열처리 시간은 570℃에서 24시간이 소요되었으나, 교번자장결정화의 경우, 같은 온도에서 20분이 소요되었다.

• Journal of Information Display
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• 제4권1호
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• pp.34-37
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• 2003

We investigate the solid phase crystallization of amorphous Si films on glass substrates under alternating magnetic field induction. The kinetics of crystallization are found to be greatly enhanced by alternating magnetic field. While complete crystallization takes heat treatment of more than 14 hours at 570$^{\circ}C$, it can be reduced by applying the megnetic field to 20 minutes. It is assumed that the enhancement of crystallization is associated with an electromotive force voltage generated by alternating magnetic field. This electric field applied in the amorphous Si may possibly be the reason for acceleration of the atomic mobility of crystallization through the modification of atomic potentials

• Korean Membrane Journal
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• 제9권1호
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• pp.27-33
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• 2007

PVDF membrane formation via TIPS was performed for PVDF/DBP and PVDF/DMP systems. PVDF/DBP system showed solid-liquid phase separation behavior, while PVDF/DMP system has liquid-liquid phase separation characteristic as well as solid-liquid phase separation characteristic. PVDF contents and cooling conditions had great influence on structure, and the effects of each parameter were examined. Spherulitic structure was obtained due to the dominant PVDF crystallization. Diluent rejected to the outside of spherulite occupied the surface of the PVDF spherulites to result in the microporous spherulite formation and micro-void between spherulites. PVDF/DMP system had competitive solid-liquid and liquid-liquid phase separation depending on the cooling path.

• 한국진공학회지
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• 제4권1호
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• pp.77-84
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• 1995

LCD용 다결정 실리콘 TFT의 제조에 요구되는 고품위의 다결정 실리콘 박막을 60미만의 저온 공정으로 제조하는 기술로 비정질 박막의 고상 결정화(solid phase crystallization) 가 유망하다. 본 연구에서는 고진공 화학증착기를 이용하여 증착된 비정질 실리콘 막의 고상결정거동에 대해 연구하였다. 고상 결정화 속도 및 결정화 후의 결정성(결정립 크기 및 결함 밀도) 화학증착시의 증착가스의 종류(SiH4 혹은 Si2H6), 공정 압력, 증착 온도 등에 민감한 영향을 받으며 Si2H6가스의 사용, 증착 압력의 증가, 증착온도의 감소는 최종 결정립의 크기를 현저히 증가시킨다. 또한 증착전의 기초 진공도를 높임으로써 반응기 잔류 가스에 의한 산소나 탄소 등의 막내 유입이 감소되어 결정화 속도가 증가하고 결정성이 향상되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 추계학술대회 논문집
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• pp.89-93
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• 1995

Effects of hydrogenation in amorphous silicon rile growths on Solid Phase Crystallization (SPC) was investigated using x-ray diffractometry, energy dispersive Spectroscopy, and Raman spectrum. Interdiffusion of barium(Ba) and aluminum(Al) compounds of corning substrate was observed in both of rf sputtering and LFCVD films under the low temperature(580$^{\circ}C$) annealing. Low degree of crystallinity resulted from the interdiffusion was obtained. Highly applicable degree of crystallinity was obtained through the mechanical damage induced surface activation on amorphous silicon films. X-ray diffraction intensity of (111) orientation was used to characterize the degree of crystallinity of SPC. Nucleation and growth rate in SPC could be controllable through the employed surface treatment. IIydrogenated LPCVD films showed the superior crystallinity to non-hydrogenated sputtering films. Insignificant effects of activation treatment in sputtered film was of activation treatment in sputtered film was observed on SPC.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.60-61
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• 2007

In this paper, the p-channel poly Si thin-film transistors (Poly-Si TFT's) using formed by solid phase crystallization (SPC) on glass substrate were fabricated. And we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's to indicate non-volatile memory (NVM) effect. Poly-Si TFT is investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, on/off current ratio. NVM characteristics is showed by measuring the threshold voltage change of TFT through I-V characteristics.

• 한국전기전자재료학회논문지
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• 제22권6호
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• pp.462-465
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• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.