• Journal of Mechanical Science and Technology
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• v.19 no.5
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• pp.1065-1071
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• 2005

In this study, residual stress distribution in multi-stacked film by MEMS (Micro-Electro Mechanical System) process is predicted using Finite Element method (FEM). We evelop a finite element program for residual stress analysis (RESA) in multi-stacked film. The RESA predicts the distribution of residual stress field in multi-stacked film. Curvatures of multi­stacked film and single layers which consist of the multi-stacked film are used as the input to the RESA. To measure those curvatures is easier than to measure a distribution of residual stress. To verify the RESA, mean stresses and stress gradients of single and multi layers are measured. The mean stresses are calculated from curvatures of deposited wafer by using Stoney's equation. The stress gradients are calculated from the vertical deflection at the end of cantilever beam. To measure the mean stress of each layer in multi-stacked film, we measure the curvature of wafer with the left film after etching layer by layer in multi-stacked film.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.549-552
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• 1987

TO INCREASE THE CELL CAPACITANCE Of SMALL GEOMETRY DRAMS. HIGH DIELECTRIC MATERIAL HAS BEEN USED RECENTLY. THE PURPOSE Of THIS WORK IS TO INVESTIGATE THE STRUCTURAL AND ELECTRICAL CHARACTERISTICS Of SiO2/Si3N4/SiO2 STACKED FILM UTILIZING HIGH DIELECTRIC MATERIAL Si3N4(${\epsilon}=7.5$). IN RESULT, THE DIELECTRIC CONSTANT Of STACKED FILM IS 4.0 - 5.0 AND CAPACITANCE AND BREAKDOWN FIELD WERE MORE INCREASED THAN THOSE Of SiO2 FILM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.73-78
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• 1991

In this study of stacked type film chip capacitor, the important parameters are heat-treated temperature, pressure and time. We measured the temperature dependence of dielectric properties and dissipation factor and the frequency dependence of dielectric properties, dissipation factor, ESR(Equivalent Series Resistance) and impedance in stacked type film capacitor. As a result, the best conditions of heat-treated temperature, pressure and time were proved to be 130$^{\circ}C$, 10kg/$\textrm{cm}^2$ and 3hrs, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.184-187
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• 2002

In this work, the electrical characteristics of organic thin film transistors with the stacked organic gate insulators have been studied. PVP(Polyvinylphenol) and polystyrene were used as gate insulating materials. Both the high dielectric constant of PVP and better insulating capability of polystyrene were compensatorily adopted in two different stacking orders of PVP-polystyrene and polystyrene-PVP. The output characteristics of the device with the stacked gate insulator showed substantial improvement compared with those of the devices with either PVP or polystyrene gate insulator: Furthermore, these stacked organic gate insulators can differently affect the TFT characteristics with the stacking orders. The electrical properties of TFTs with organic gate insulators stacked in different orders are discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.118-119
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• 2007

High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

• Current Photovoltaic Research
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• v.7 no.1
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• pp.1-8
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• 2019

The $Cu(In,Ga)Se_2$ (CIGS) thin film obtained by two-step process (metal deposition and Se annealing) has a rough surface morphology and many voids at the CIGS/Mo interface. To solve the problem a precursor that contains Se was employer by depositing a (In,Se)/(Cu,Ga) stacked layer. We devised a two-step annealing (vacuum pre-annealing and Se annealing) for the precursor because direct annealing of the precursor in Se environment resulted in the small grains with unwanted demarcation between stacked layers. After vacuum pre-annealing up to $500^{\circ}C$ the CIGS film consisted of CIGS phase and secondary phases including $In_4Se_3$, InSe, and $Cu_9(In,Ga)_4$. The secondary phases were completely converted to CIGS phase by a subsequent Se annealing. A void-free CIGS/Mo interface was obtained by the two-step annealing process. Especially, the CIGS film prepared by vacuum annealing $450^{\circ}C$ and subsequent Se annealing $550^{\circ}C$ showed a densely-packed grains with smooth surface, well-aligned bamboo grains on the top of the film, little voids in the film, and also little voids at the CIGS/Mo interface. The smooth surface enhanced the cell performance due to the increase of shunt resistance.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1546-1548
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• 2002

In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.381-382
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• 2007

IZO/Ag/IZO (IAI) anode films for flexible organic light emitting diodes (OLEDs) were grown on PC (polycarbonate) substrate using DC sputter (IZO) and thermal evaporator (Ag) systems as a function of Ag thickness. To investigate electrical and optical properties of IAI stacked films, 4-point probe and UV/Vis spectrometer were used, respectively. From a IAI stacked film with 12nm-thick Ag, sheet resistance of $6.9\;{\Omega}/{\square}$ and transmittance of above 82 % at a range of 500-550 nm wavelength were obtained. In addition, structural and surface properties of IAI stacked films were analyzed by XRD (X-ray diffraction) and SEM (scanning electron microscopy), respectively. Moreover, IAI stacked films showed dramatically improved mechanical properties when subjected to bending both as a function of number of cycles to a fixed radius. Finally, OLEDs fabricated on both flexible IAI stacked anode and conventional ITO/Glass were fabricated and, J-V-L characteristics of those OLEDs were compared by Keithley 2400.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• Macromolecular Research
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• v.14 no.1
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• pp.38-44
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• 2006

Vacuum deposited copper phthalocyanine (CuPc) was placed as a thin interlayer between indium tin oxide (ITO) electrode and a hole transporting layer (HTL) in a multi-layered, organic, light-emitting diode (OLEOs). The well-stacked CuPc layer increased the stability and efficiency of the devices. Thermal annealing after CuPc deposition and magnetic field treatment during CuPc deposition were performed to obtain a stacked-CuPc layer; the former increased the stacking density of the CuPc molecules and the alignment of the CuPc film. Thermal annealing at about 100$^{circ}C$ increased the current flow through the CuPc layer by over 25$\%$. Surface roughness decreased from 4.12 to 3.65 nm and spikes were lowered at the film surface as well. However, magnetic field treatment during deposition was less effective than thermal treatment. Eventually, a higher luminescence at a given voltage was obtained when a thermally-annealed CuPc layer was placed in the present, multi-layered, ITO/CuPc/NPD/Alq3/LiF/AI devices. Thermal annealing at about 100$^{circ}C$ for 3 h produced the most efficient, multi-layered EL devices in the present study.