• Journal of the Korea Society for Simulation
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• v.8 no.4
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• pp.1-8
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• 1999

This paper proposes an ATM switch architecture called Output Queued Batcher-Banyan switch (OQBBS). It consists of a Sorting Module, Expanding Module, and Output Queueing Modules. The principles of channel grouping and output queueing are used to increase the maximum throughput of an ATM switch. One distinctive feature of the OQBBS is that multiple cells can be simultaneously delivered to their desired output. The switch architecture is shown to be modular and easily expandable. The performance of the OQBBS in terms of throughput, cell delays, and cell loss rate under uniform random traffic condition is evaluated by computer simulation. The throughput and the average cell delay are close to the ideal performance behavior of a fully connected output queued crossbar switch. It is also shown that the OQBBS meets the cell loss probability requirement of $10^{-6}$.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.12B no.1
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• pp.37-43
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• 2002

This paper proposes a new zero-current switching (ZCS) pulse-width modulation (PWM) switch cell that has no additional conduction loss of the main switch. In this cell, the main switch and the auxiliary switch turn on and turn off under zero current condition. The diodes commutate softly and the reverse recovery problems are alleviated. The conduction loss and the current stress of the main switch are minimized, since the resonating current for the soft switching does not flow through the main switch. Based on the proposed ZCS PWM switch cell, a new family of dc to dc PWM converters is derived. The new family of ZCS PWM converters is suitable for the high power applications employing IGBTs. Among the new family of dc to dc PWM converters, a boost converter was taken as an example and has been analyzed. Design guidelines with a design example are described and verified by experimental results from the 2.5㎾ prototype boost converter operating at 40KHz.

• Journal of Power Electronics
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• v.1 no.2
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• pp.71-77
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• 2001

This paper proposes a new zero-current switching (ZCS) pulse-width modulation (PWM) switch cell that has no additional conduction loss of the main switch. In this cell, the main switch and the auxiliary switch turn on and turn off under zero current condition. The diodes commutate softly and the reverse recovery problems are alleviated. The conduction loss and the current stress of the main switch are minimized, since the resonating current stress of the main switch are minimized, since the resonating current for the soft switching does not flow through the main switch. Based on the proposed ZCS PWM switch cell, a new family of DC to DC PWM converters is derived. The new family of ZCS PWM converters is suitable for the high power applications employing IGBTs. Among the new family of DC to DB PWM converters, a boost converter was taken as an example and has been analyzed. Design guidelines with a design example are described and verified by experimental results from the 2.5 kW prototype converter operating at 40 kHz.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.950-952
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• 2001

This paper proposes a new zero-current transition (ZCT) pulse-width modulation (PWM) switch cell that overcomes the limitations of the conventional ZCT converters. The proposed ZCT cell provides zero-current-switching (ZCS) condition for the main switch and the auxiliary switch. The conduction loss and current stress of the main switch are minimized, since the circulating current for the soft switching does not flow through the main switch. The proposed ZCT PWM switch cell is suitable for the high power applications employing IGBTs. Design guidelines with a design example are described and verified by experimental results from the 1 kW prototype boost converter operating at 70kHz.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.289-440
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• 1998

This paper describes an interconnection network structure which transports information among processors through a high speed ATM switch. To efficiently use the high speed ATM switch for the message-based multiprocessor, we implemented the cell router that performs multiplexing and demultiplexing of cells from/to processors. In this system, we use the expanded internal cell format including 3bytes for switch routing information. This interconnection network has 3 stage routing strategies: ATM switch routing using switch routing information, cell router routing using a virtual path identifier (VPI) and cell reassembly routing using a virtual channel indentifier (VCI). The interconnection network consists of the NxN folded switch and N cell routers with the M processor interface. Therefore, the maximum number of NxM processors can be interconnected for message communication. This interconnection network using the ATM switch makes a significant improvement in terms of message passing latency and scalability. Additionally, we evaluated the transmission overhead in this interconnection network using ATM switch.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.273-276
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• 1998

This paper proposes a new Asynchronous Transfer Mode(ATM) switch architecture for the Broadband ISDN. The proposed switch has the architecture to prohibit the out-of-sequence in shared buffer switch system with being fixed buffer size in the out-buffered large scale ATM Switch System. then in this paper proposes cell resequence algorithm to decrease the out-of-sequence problem. also, we studied the out-of-sequence problem that was occurred by the cell transfer delay and the cell overflow due to the fixed buffer size when cell resequenced and we propose to implement optimal ACFIFO(Address Counter First In First Out) buffer size which has the minimized cell loss.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1922-1931
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• 1999

A multicast traffic’s feature is the function of providing a point to multipoints cell transmission, which is emerging from the main function of ATM switch. However, when a conventional point-to-point switch executes a multicast function, the excess load is occurred because unicast cell as well as multicast cell passed the copy network. Additionally, due to the excess load, multicast cells collide with other cells in a switch. Thus a deadlock that losses cells raises, extremely diminishes the performance of switch. An input queued switch also has a defect of the HOL (Head of Line) blocking that less lessens the performance of the switch. In the proposed multicast switch, we use shared memory switch to reduce HOL blocking and deadlock. In order to decrease switch’s complexity and cell's processing time, to improve a throughput, we utilize the method that routes a cell on a separated paths by traffic pattern and the scheduling algorithm that processes a maximum 2N cell at once in the control part. Besides, when cells is congested at an output port, a cell loss probability increases. Thus we use the Output Memory (OM) to reduce the cell loss probability. And we make use of the method that stores the assigned memory (UM, MM) with a cell by a traffic pattern and clears the cell of the Output memory after a fixed saving time to improve the memory utilization rate. The performance of the proposed switch is executed and compared with the conventional policy under the burst traffic condition through both the analysis based on Markov chain and simulation.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.23-28
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• 2007

In this paper, we propose ATM switch structure including AAL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of AAL cells which consist of AAL type 1, AAL type 2, AAL type 3/4, and AAL type 5 cells. We propose two switch fabric methods; One supports the AAL type 2 cell processing per input port, the other global AAL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a strong point for easy implementation and extensibility. The proposed ATM switch fabric architecture is applicable to mobile communication, narrow band services over ATM network.

• Journal of Electrical Engineering and Technology
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• v.11 no.2
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• pp.367-376
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• 2016

This paper presents a cell balancing method for a single switch flyback converter with a multi-winding transformer. The conventional method using a flyback converter with a multi-winding transformer is simple and easy to control, but the voltage of each secondary winding coil might be non-uniform because of the unequal effective turn-ratio. In particular, it is difficult to control the non-uniform effect using turn-ratios because secondary coil has a limited number of turns. The non-uniform secondary voltages disturb the cell balancing procedure and induce an unbalance in cell voltages. Individual cell control by adding a switch for each cell can reduce the undesirable effect. However, the circuit becomes bulky, resulting in additional loss. The proposed method here uses the conventional flyback converter with an adjustment made to the output filters of the cells, instead of the additional switch. The magnitude of voltage applied to a particular cell can be reduced or increased according to the adjusted filter and the selected switching frequency. An analysis of the conventional converter configuration and the filter design method reveals the possibility of adequate cell balancing control without any additional switch on the secondary side.

• Journal of the Korea Society for Simulation
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• v.8 no.1
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• pp.51-61
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• 1999

A cell scheduling method of Queue for the ATM switch is proposed and simulated. In this paper, we present the cell scheduling method proper to the proposed queue and the improved queue with Queue Sharing(QS) structure for CBR, VBR, ABR traffic. The proposed QS structure minimizes the CLS(Cell Loss Ratio) of ABR traffic and decreases the CLR of bursty VBR traffic. Also we propose a cell scheduling method using VRR(Variable Round Robin) scheme proper to the high-speed(ATM) switch. The VRR scheme provides a fairness in terms of service chance for the queues in the ATM switch as well as QOS of their cell delay characteristic of CBR and VBR traffic, QOS of ABR CLR. The simulation results show the proposed method achieves excellent CLR and average cell delay performance for the various ATM traffic services in the Queue Sharing structure.