• Title, Summary, Keyword: synchronous generator

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A Study on 3[kW] PMA-RSG Optimal Design for Mobile Power Supply (이동형 전원장치용 3[kW] PMA-RSG의 최적 설계에 대한 연구)

  • Baik, Jei-Hoon;Toliyat, Hamid A.;Kim, Nam-Hun
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.23 no.6
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    • pp.109-117
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    • 2009
  • In this paper, an analytical model using equivalent magnetic circuits for the PMA-SynRG is presented. The lumped parameter model (LPM) is developed from machine geometry, stator winding and machine operating specifications. By the LPM, magnetic saturation of rotor bridges is incorporated into model and it provides effective means of predicting machine performance for a given machine geometry. The LPM is not as accurate as finite element analysis but the equivalent magnetic circuits provide fast means of analyzing electromagnetic characteristics of PMa-SynRG. It is the main advantage to find the initial design and optimum design. The initial design of PMa_RSG is performed by LPM model and FEM analysis, and the final PMA-RSG design is optimized and identified by FEM analysis considering actual machine design. The linear LPM and the nonlinear LPM are programmed using MATLAB and all of machine parameters are calculated very quickly. To verify justification of the proposed design of PMa-RSM, back-EMF is measured.

Distribution Feeder Aspects of a Variable Speed Wind Turbine in Voltage Fluctuations and Harmonics (가변속 풍력터빈이 연계된 배전선로의 전압변동 및 고조파 영향)

  • 김슬기;김응상
    • Journal of Energy Engineering
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    • v.12 no.4
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    • pp.309-319
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    • 2003
  • The main purpose of this paper is to present a simulation model for assessing the impacts of a variable speed wind turbine (VSWT) on the distribution network and perform a simulation analysis of volt-age profiles and harmonics along the wind turbine installed feeder using the presented model. The modeled wind energy conversion system consists of a fixed pitch wind turbine and a permanent-magnet synchronous generator, in which a controllable power electronics inverter performs variable speed operation and reactive power output control. Impact analysis on voltage profiles and harmonics of a VSWT-installed distribution feeder is addressed and simulated in terms of steady state and dynamic behaviors. Various capacities and different modes of variable speed wind turbines are simulated and investigated. Case studies demonstrate how feeder voltages are influenced by capacity and control modes of wind turbines and changes in wind speed under various network conditions, and show harmonic impacts on the feeder. Modeling and simulation analysis is based on PSCAD/EMTDC a software package.

Modeling and Analysis of Control Scheme for Voltage Source Inverter Based Grid-connection of Wind Turbine (전압원인버터를 이용한 계통연계형 풍력발전의 출력제어 모의 및 해석)

  • 김슬기;김응상
    • Journal of Energy Engineering
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    • v.12 no.2
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    • pp.154-163
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    • 2003
  • Grid connection essentially requires a wind energy conversion system (WECS) to not only supply adequate power responding to constantly varying wind speed but also provide a specified level of voltage magnitude and frequency that is acceptable in the electric power network. To satisfy such requirements, appropriate control schemes of a wind turbine to be connected to the power grid should be employed. This paper presents an output control strategy of a grid-connected wind power generation, which consists of a fixed-pitch wind turbine, a synchronous generator and a AC-DC-AC component with a voltage source inverter built in, and performs modelling and analysis of the strategy using PSCAD/EMTDC, an electromagnetic transient analysis software. Real power output control of the voltage source inverter is implemented to extract the maximum energy from wind speed inputted through wind blades and reactive power control, to keep the terminal voltage of WECS at a specific level. SPWM switching method is used to reduce the harmonics and maintain 60 ㎐ of the output frequency. The wind turbine performance and output corresponding to wind variation and the terminal load change is simulated and analysed.

A design on low-power and small-area EEPROM for UHF RFID tag chips (UHF RFID 태그 칩용 저전력, 저면적 비동기식 EEPROM 설계)

  • Baek, Seung-Myun;Lee, Jae-Hyung;Song, Sung-Young;Kim, Jong-Hee;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.12
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    • pp.2366-2373
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    • 2007
  • In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

Development of Digital Transceiver Unit for 5G Optical Repeater (5G 광중계기 구동을 위한 디지털 송수신 유닛 설계)

  • Min, Kyoung-Ok;Lee, Seung-Ho
    • Journal of IKEEE
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    • v.25 no.1
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    • pp.156-167
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    • 2021
  • In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

A PN-code Acquisition method Using Array Antenna Systems for CDMA2000 1x (CDMA2000 1x용 배열 안테나 시스템에서 PN 동기 획득 방법)

  • Jo, Hee-Nam;Yun, Yu-Suk;Choi, Seung-Won
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.8
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    • pp.33-40
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    • 2005
  • This paper presents a structure of the searcher using a diversity in array antenna systems operating in the cdma2000 1x signal environments. The new technique exploits the fact that the In-phase and quadrature components of interferers can respectively be viewed as an independent gaussian noise at each antnna element in most practical cdma signal environments. The proposed PN acquisition scheme is a singles-dwell PN acquisition system consisting of two stages, that is, the searching stage and the verification stage. The searching stage independently correlates the receiver multiple signals with PN generator of each antenna element for obtaining the synchronous energy at the entire region. Then, the searching results of each antenna element are non-coherently combinind. The verification stage compares the searching energy with the optimal threshold, which is predesigned in the lock detector, and decides whether the acquisition is successful or fail. In this paper, we analyzed the effect of tile diversity order to determine the mean acquisition time. In general, it is known that the mean acquisition time significantly decrease as the number of antenna elements increases. But, as the diversity order goes up, the enhancement of the performance is saturated. Therefore, to decrease the mean acquisition time of the searcher, we must design the optimal array antenna systems by considering the operating SNR range of the receiver, the probability of detection $P_D$ and that of false alarm $P_{FA}$ . The Performance of the proposed PN acquisition scheme is analyzed in frequency selective Rayleigh fading channels. In this paper, the effect of the number of antenna elements on PN acquisition scheme is shown according to the probability of detection $P_D$ and that of false alarm $P_{FA}$.