• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• ETRI Journal
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• v.33 no.5
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• pp.822-825
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• 2011

Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 ${\mu}m$ CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

• Journal of Korea Multimedia Society
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• v.25 no.6
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• pp.783-792
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• 2022

Versatile Video Coding (VVC) is the latest video coding standard, which had been developed by the Joint Video Experts Team (JVET) of ITU-T Video Coding Experts Group (VCEG) and ISO/IEC Moving Picture Experts Group (MPEG) in 2020. Although VVC can provide powerful coding performance, it requires tremendous computational complexity to determine the optimal block structures during the encoding process. In this paper, we propose a fast ternary tree decision method using two neural networks with 7 nodes as input vector based on the multi-layer perceptron structure, names STH-NN and STV-NN. As a training result of neural network, the STH-NN and STV-NN achieved accuracies of 85% and 91%, respectively. Experimental results show that the proposed method reduces the encoding complexity up to 25% with unnoticeable coding loss compared to the VVC test model (VTM).

• ETRI Journal
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• v.39 no.4
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• Journal of Broadcast Engineering
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• v.27 no.3
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• pp.361-368
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• 2022

Quaternary tree plus multi-type tree (QT+MTT) structure was adopted in the Versatile Video Coding (VVC) standard as a block partitioning tool. QT+MTT provides excellent coding gain; however, it has huge encoding complexity due to the flexibility of the binary tree (BT) and ternary tree (TT) splits. This paper proposes a fast inter coding unit (CU) partitioning algorithm for BT and TT split types based on prediction accuracy functions using the mean of the absolute error (MAE). The MAE-based decision model was established to achieve a consistent time-saving encoding with stable coding loss for a practical low complexity VVC encoder. Experimental results under random access test configuration showed that the proposed algorithm achieved the encoding time saving from 24.0% to 31.7% with increasing luminance Bjontegaard delta (BD) rate from 1.0% to 2.1%.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.1
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• pp.11-19
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• 2020

IoT has been consistently used in various fields such as smart home, wearables, and healthcare. Since IoT devices are small terminals, relatively simple wireless communication protocols such as IEEE 802.15.4 and ISO 18000 series are used. In this paper, we designed the 802.15.4q 2.4 GHz TASK physical layer. Physical protocol data unit of TASK supports bit-level interleaving and shortened BCH encoding. It is spread by unique ternary sequences. There are four spreading factors to choose the data rate according to the communication channel environment. The TASK physical layer was designed using verilog-HDL and verified through the loop-back test of the transceiver. The designed TASK physical layer was implemented in a fpga and tested using MAXIM RFICs. The PER was about 0% at 10 dB SNR. It is expected to be used in small, low power IoT applications.

• Journal of applied mathematics & informatics
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• v.29 no.3_4
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• pp.547-562
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• 2011

We establish a new formalism of the non-periodic autocorrelation function (NPAF) of two sequences, which is suitable for the computation of the NPAF of any two sequences. It is shown, that this encoding of NPAF is efficient for sequences of small weight. In particular, the check for two sequences of length n having weight w to have zero NPAF can be decided in $O(n+w^2{\log}w)$. For n > w^2{\log}w$, the complexity is O(n) thus we cannot expect asymptotically faster algorithms.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.