• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.270-274
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• 2016

This article investigates the use of the Gaussian-channel doping profile for the control of the short-channel effects in the double-gate MOSFET whereby a two-dimensional (2D) quantum simulation was used. The simulations were completed through a self-consistent solving of the 2D Poisson equation and the Schrodinger equation within the non-equilibrium Green’s function (NEGF) formalism. The impacts of the p-type-channel Gaussian-doping profile parameters such as the peak doping concentration and the straggle parameter were studied in terms of the drain current, on-current, off-current, sub-threshold swing (SS), and drain-induced barrier lowering (DIBL). The simulation results show that the short-channel effects were improved in correspondence with incremental changes of the straggle parameter and the peak doping concentration.

• Korean Journal of Materials Research
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• v.18 no.5
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• pp.272-276
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• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.130-133
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• 2010

This paper presents a study of the influence of variation of counter doping thickness on short channel effect in symmetric double-gate (DG) nano MOSFETs. Short channel effects are estimated from the computed values of current-voltage (I-V) characteristics. Two dimensional Quantum transport equations and Poisson equations are used to compute DG MOSFET characteristics. We found that the transconductance ($g_m$) and the drain conductance ($g_d$) increase with an increase in p-type counter-doping thickness ($T_c$). Very high value of transconductance ($g_m=38\;mS/{\mu}m$) is observed at 2.2 nm channel thickness. We have established that the threshold voltage of DG MOSFETs can be tuned by selecting the thickness of counter-doping in such device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.879-882
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• 2015

In this work, we have analyzed the characteristics of vertical nanowire GAA MOSFET according to channel width and the type of channel doping through the simulation. First, we compared and analyzed the characteristics of designed structures which have tilted shapes that ends of drains are fixed as 20nm and ends of sources are 30nm, 50nm, 80nm and 110nm. Second, we designed the rectangular structure which has uniform width of drain, channel and source as 50nm. We used it as a standard and designed trapezoidal structure which is tilted so that the end of drain became 20nm and reverse trapezoidal structure which is tilted so that the end of source became 20nm. We compared and analyzed the characteristic of above three structures. For the last, we used the rectangular structure, divided its channel as five parts and changed the type of the five parts of doping concentration variously. In the first simulation, when the channel width is the shortest, in the second, when the structure is trapezoid, in the third, when the center of channel is high doped show the best characteristics.

• Transactions on Electrical and Electronic Materials
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• v.7 no.3
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• pp.99-102
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• 2006

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.140-140
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• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.199-199
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• 2011

Recently, Thin film transistors (TFTs) with amorphous oxide semiconductors (AOSs) can offer an important aspect for next generation displays with high mobility. Several oxide semiconductor such as ZnO, $SnO_2$ and InGaZnO have been extensively researched. Especially, as a well-known binary metal oxide, tin oxide ($SnO_2$), usually acts as n-type semiconductor with a wide band gap of 3.6eV. Over the past several decades intensive research activities have been conducted on $SnO_2$ in the bulk, thin film and nanostructure forms due to its interesting electrical properties making it a promising material for applications in solar cells, flat panel displays, and light emitting devices. But, its application to the active channel of TFTs have been limited due to the difficulties in controlling the electron density and n-type of operation with depletion mode. In this study, we fabricated staggered bottom-gate structure $SnO_2$-TFTs and patterned channel layer used a shadow mask. Then we compare to the performance intrinsic $SnO_2$-TFTs and doping hafnium $SnO_2$-TFTs. As a result, we suggest that can be control the defect formation of $SnO_2$-TFTs by doping hafnium. The hafnium element into the $SnO_2$ thin-films maybe acts to control the carrier concentration by suppressing carrier generation via oxygen vacancy formation. Furthermore, it can be also control the mobility. And bias stability of $SnO_2$-TFTs is improvement using doping hafnium. Enhancement of device stability was attributed to the reduced defect in channel layer or interface. In order to verify this effect, we employed to measure activation energy that can be explained by the thermal activation process of the subthreshold drain current.