• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.6
• /
• pp.678-684
• /
• 2015

Near-threshold computing (NTC) is now regarded as a promising candidate for innovative power reduction, which cannot be achieved with conventional super-threshold computing (STC). However, performance degradation and vulnerability to process variation in the NTC regime are the primary concerns. In this paper, we propose a voltage- and frequency-tuning methodology for mitigating the process-variation-induced problems in NTC-based manycore architectures. To implement the proposed methodology, we build up multiple-voltage multiple-frequency (MVMF) islands and apply a voltage-frequency tuning algorithm based on the critical-path monitoring technique to reduce the effects of process variation and maximize energy efficiency in the post-silicon stage. Experimental results show that the proposed methodology reduces overall power consumption by 8.2-20.0%, compared to existing methods in variation-sensitive NTC environments.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.1
• /
• pp.135-141
• /
• 2014

In this paper, the device design guideline to reduce the threshold voltage variation with fin width in junctionless MuGFET has been suggested. It has been observed that the threshold voltage variation was increased with increase of fin width in junctionless MuGFETs. To reduce the threshold voltage variation with fin width in junctionless MuGFETs, 3-dimensional device simulation with different gate dielectric materials, silicon film thickness, and an optimized fin number has been performed. The simulation results showed that the threshold voltage variation can be reduced by the gate dielectric materials with a high dielectric constant such as $La_2O_3$ and the silicon film with ultra-thin thickness even though the fin width is increased. Particularly, the reduction of the threshold voltage variation and the subthreshold slope by reducing the fin width and increasing the fin numbers is known the optimized device design guideline in junctionless MuGFETs.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.3
• /
• pp.279-284
• /
• 2014

This paper proposes a novel OLED pixel circuit to compensate the threshold voltage variation of p-channel low temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed 5-TFT OLED pixel circuit consists of 4 switching TFTs, 1 OLED driving TFT and 1 capacitor. One frame of the proposed pixel circuit is divided into initialization period, threshold voltage sensing and data programming period, data holding period and emission period. SmartSpice simulation results show that the maximum error rate of OLED current is -4.06% when the threshold voltage of driving TFT varies by ${\pm}0.25V$ and that of OLED current is 9.74% when the threshold voltage of driving TFT varies by ${\pm}0.50V$. Thus, the proposed 5T1C pixel circuit can realize uniform OLED current with high immunity to the threshold voltage variation of p-channel poly-Si TFT.

• Journal of information and communication convergence engineering
• /
• v.8 no.1
• /
• pp.107-111
• /
• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.15 no.3
• /
• pp.205-210
• /
• 2022

A novel OLED pixel circuit is proposed in this paper that uses only n-type thin-film transistors(TFTs) to improve the luminance non-uniformity of the AMOLED display caused by the threshold voltage variation of an OLED driving TFT. The proposed OLED pixel circuit is composed of 6 n-channel TFTs and 2 capacitors. The operation of the proposed OLED pixel circuit consists of the capacitor initializing period, threshold voltage sensing period of an OLED·driving TFT, image data voltage writing period, and OLED·emitting period. As a result of SmartSpice simulation, when the threshold voltage of·OLED·driving TFT varies from 1.2 V to 1.8 V, the proposed OLED pixel circuit has a maximum current error of 5.18 % at IOLED = 1 nA. And, when the OLED cathode voltage rises by 0.1 V, the proposed OLED pixel circuit has very little change in the OLED current compared to the conventional OLED pixel circuit. Therefore, the proposed pixel circuit exhibits superior compensation characteristics for the threshold voltage variation of an OLED driving TFT and the rise of the OLED cathode voltage compared to the conventional OLED pixel circuit.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.3
• /
• pp.132-138
• /
• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• Journal of Sensor Science and Technology
• /
• v.23 no.2
• /
• pp.114-121
• /
• 2014

We report a polysilicon active area membrane field effect transistor (PSAFET) pressure sensor for low stress deflection of membrane. The PSAFET was produced in conventional FET semiconductor fabrication and backside wet etching. The PSAFET located at the front side measured pressure change using 300 nm thin-nitride membrane when a membrane was slightly strained by the small deflection of membrane shape from backside with any physical force. The PSAFET showed high sensitivity around threshold voltage, because threshold voltage variation was composed of fractional function form in sensitivity equation of current variation. When gate voltage was biased close to threshold voltage, a fractional function form had infinite value at $V_{tn}$, which increased the current variation of sensitivity. Threshold voltage effect was dominant right after the PSAFET was turned on. Narrow transistor channel established by small current flow was choked because electron could barely cross drain-source electrodes. When gate voltage was far from threshold voltage, threshold voltage effect converged to zero in fractional form of threshold voltage variations and drain current change was mostly determined by mobility changes. As the PSAFET fabrication was compatible with a polysilicon FET in CMOS fabrication, it could be adapted in low pressure sensor and bio molecular sensor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2022.10a
• /
• pp.118-120
• /
• 2022

This paper investigated the change of threshold voltage according to the influence of work-function variation (WFV) of metal gate in the device structure of monolithic 3-dimension inverter (M3DINV). In addition, in order to investigate the change in threshold voltage according to the electrical coupling of the NMOS stacked on the PMOS, the gate voltages of PMOS were applied as 0 and 1 V and then the electrical coupling was investigated. The average change in threshold voltage was measured to be 0.1684 V, and they standard deviation was 0.00079 V.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.35 no.7
• /
• pp.278-284
• /
• 1986

Double-diffused metal oxide power semiconductor field effect transistors are used extensively in recent years in various circuit applications. The temperature variation of the drain current at a fixed bias shows both positive and negative resistance characteristics depending on the gate threshold voltage and gate-to source bias votage. In this paper, the decision method of the gate crossover voltage by the temperature variation and a new method to determine the gate threshold voltage graphecally are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.8
• /
• pp.1-5
• /
• 2009

A new pixel circuit for Active Matrix Organic Light Emitting Diodes (AMOLEDs), based on the polycrystalline silicon thin film transistors (Poly-Si TFTs), was proposed and verified by SMART SPICE simulation. One driving and six switching TFTs and one storage capacitor were used to improve display image uniformity without any additional control signal line. The proposed pixel circuit compensates an inevitable threshold voltage variation of Poly-Si TFTs and also compensates the degradation of OLED at low power supply voltage($V_{DD}$). The simulation results show that the proposed pixel circuit successfully compensates the variation of OLED driving current within 0.8% compared with 20% of the conventional pixel circuit.