• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.37-44
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• 2003

A distortion suppression technology for employing multiple inputs in 3n＋1 type current mode Max circuit is proposed using the adjustment of transconductance. If the number of input blocks of the current mode Max circuit increases, the high frequency distortion in the output signal grows. In this paper, it has been disclosed that the distortion in the multiple input Max circuit is proportional to such accumulated parasitic capacitance, to the derivative of the output signal and also to tile inverse of transconductance of the common diode-connected transistor. The proposed idea is by employing as larger transconductance of the common diode-connected transistor as possible. The effectiveness of the proposed idea has been proved through the HSPICE simulation for the current mode Max circuits with various numbers of input signals.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1644-1650
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• 2009

An improved guarding circuit is applied to a transconductance driven-right-leg circuit to decrease common-mode current at measurement electrodes due to power-line interference. After showing conventional guarding circuit is instable due to gain-peaking when used with a transconductance DRL circuit, the effect of the proposed guarding circuit modified to suppress the gain-peaking by inserting a series resistor between shields and a shield driver was analyzed. It is shown that, besides stability, the proposed guarding circuit provides two other advantages: 1) The gain of the shield driver can be set to be unit nominally. 2) The loop gain of the transconductance DRL loop can be increased due to pole-zero canceling. The proposed circuit was implemented and the advantages were confirmed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.563-566
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• 1988

A current-controlled CMOS operational transconductance amplifier(OTA), whose transconductance is directly proportional to the DC bias current, has been developed for many electronic circuit applications. It features that its transconductance is insensitive to temperature unlike that of the bipolar OTA. This property makes it possible to use the proposed OTA as a basic buliding block in electrically variable circuit design. The SPICE simulation shows that the conversion sensitivity of the circuit is 44.62 mv /${\mu}A$ and the linearity error less than 0.54 % over a bias current range from 2 ${\mu}A$ to 120 ${\mu}A$ when the output is loaded with a 1${\Omega}$ resistor.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1053-1056
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• 2003

A distortion suppression technology for employing multiple inputs in 3n+1 type current mode Max circuit is proposed using the adjustment of transconductance. If the number of inputs in current mode Max circuit increases, the high frequency distortion in the output signal grows. In this paper, it has been disclosed that the distortion in the multiple input Max circuit is proportional to sum of parasitic capacitance in input terminals, to the derivative of the output signal and also to the inverse of transconductance of the common diode-connected transistor. The proposed idea is by employing as larger transconductance of the common diode-connected transistor as possible. The effectiveness of the proposed idea has been proved through the HSPICE simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.4
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• pp.274-280
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• 2001

This paper presents transconductance (g$\_$m/( characteristics of GaAs MESFET's at high temperatures ranging from room temperature to 350$\^{C}$. GaAs MESFET of 0.3x750[㎛] gate dimension has been used to obtain the experimental data. Gate to source voltage(V$\_$GS/) has been controlled to obtain the temperature dependent characteristics for maximum transconductance g$\_$mmax/ of the device. Furthermore g$\_$mmax/ and expected g$\_$m/ have been traced with temperatures ranging from room temperature to 350$\^{C}$ also by compensating for C$\_$GS/ to maintain the optimum operation of the device. From the results, V$\_$GS/decreases as the operating temperature increases for optimum operation of the transconductance. Finally V$\_$GS/ has been optimized to trace g$\_$mmax/ and enhances the decreased g$\_$m/ with different temperatures.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.74-80
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• 1990

The transconductance of short channel LDD MOSFETs in the saturation region (high Vd)has shown different characteristics from that of conventional device. The transconductance in saturation regime of short channel LDD MOSFETs is reduced from maximum value at higher gate voltage. This decline is analyzed as the velocity saturation effects of carrier at LDD region but accurate analytical expressions for the drain current Idsat and the transconductance Gmsat in the saturation regime are still not in existence. Recently the drain current dependence of parasitic source resistance Rs has been modeled from the velocity saturation of carriers in LDD region. In this study, we approximate that Rmsat that Rs is linearly dependent on the applied gate voltage. Analytical expressions for Idsat and Gmsat obtained from this approximation show the same general behavior as experimental results of short channel LDD NMOSFETs.

• ETRI Journal
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• v.31 no.5
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• pp.576-584
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• 2009

A novel tunable transconductor is presented. Input transistors operate in the triode region to achieve programmable voltage-to-current conversion. These transistors are kept in the triode region by a novel negative feedback loop which features simplicity, low voltage requirements, and high output resistance. A linearity analysis is carried out which demonstrates how the proposed transconductance tuning scheme leads to high linearity in a wide transconductance range. Measurement results for a 0.5 ${\mu}m$ CMOS implementation of the transconductor show a transconductance tuning range of more than a decade (15 ${\mu}A/V$ to 165 ${\mu}A/V$) and a total harmonic distortion of -67 dB at 1 MHz for an input of 1 Vpp and a supply voltage of 1.8 V.

• ETRI Journal
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• v.42 no.4
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• pp.534-548
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• 2020

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.143-148
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• 2015

In this paper a new method is proposed for realizing active floating inductors from voltage differencing transconductance amplifier(VDTA) which is being studied nowadays. This proposed method employs only one VDTA and one transconductance for designing an active inductor from a passive floating inductor and implementing it to integrated circuits. The number of CMOS transistors can be considerably reduced from 6~18 as 1~3 gm circuits can be eliminated and even without R the design can be made, which can help in reducing the size of the circuit and power consumption. The proposed VDTA floating inductor was successfully used in constructing 1 MHz second order biquad active bandpass filter and bandwidth could be adjusted from 77kHz~1.59MHz by the changes made in gm from 6uS~20uS.