• 전기학회논문지
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• 제61권3호
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• pp.422-426
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• 2012

Transient radiation is emitted during a nuclear explosion. Transient radiation causes a fatal error in the CMOS circuit as a Upset and Latch-up. In this paper, transient radiation NMOS, PMOS, INVERTER SPICE model was proposed on the basisi of transient radiation effects analysis using TCAD(Technology Computer Aided Design). Photocurrent generated from the MOSFET internal PN junction was expressed to the current source and Latch-up phenomenon in the INVERTER was expressed to parasitic thyristor for the transient radiation SPICE model. For example, the proposed transient radiation SPICE model was applied to CMOS NAND circuit. SPICE simulated characteristics were similar to the TCAD simulation results. Simulation time was reduced to 120 times compared to TCAD simulation.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.719-721
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• 2012

본 시험은 군전자장비의 전원제어부품으로 사용되는 TPS54315소자에 대하여 과도방사선에 따른 과도응답특성인 Upset/Latch-up특성을 평가하기 시험으로 포항가속기 연구소내의 Test LINAC 조사시설을 이용하여 $1.43{\times}10^7$rad(si)/sec~$1.25{\times}10^8$rad(si)/sec 선량률 조건에서의 실측시험을 수행하였다. 시험결과 $1.0{\times}10^8$rad(si)/sec 이후 Latch-up 현상이 확인되었으며 연속펄스 인가 시 Latch-up상태에서 정상상태로 복귀하는 결과를 확인하였다. 또한 이러한 현상은 과도방사선에 의한 광전류가 내부전원 Reset로직을 트리거 시킴으로써 Latch-up상태에서의 전원바이어스를 일시적으로 차단함에 따라 발생된 것으로 본 실험을 통하여 Reset회로가 내장된 소자의 경우 일부 Latch-up현상과 동시에 Reset회로가 트리거 되는 경우 Latch-up상태에서 정상상태로 복귀되는 결과를 확인하였다.

• Journal of Electrical Engineering and Technology
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• 제8권5호
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• pp.1182-1187
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• 2013

Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

• 한국산업융합학회 논문집
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• 제5권1호
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• pp.39-43
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• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• 전기학회논문지
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• 제63권4호
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• pp.490-494
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• 2014

In this paper, a design of high-speed power-off circuit and analysis. The incidence of high-dose transient radiation into the silicon-based semiconductor element induces the photocurrent due to the creation of electron-hole pairs, which causes the upset phenomenon of active elements or triggers the parasitic thyristor in the element, resulting in latch-up. High speed power-off circuit was designed to prevent burn-out of electronic device caused by Latch-up. The proposed high speed power-off circuit was configured with the darlington transistor and photocoupler so that the power was interrupted and recovered without the need for an additional circuit, in order to improve the existing problem of SCR off when using the thyristor. The discharge speed of the high speed power interruption circuit was measured to be 19 ${\mu}s$ with 10 ${\mu}F$ and 500 ${\Omega}$ load, which was 98% shorter than before (12.8 ms).

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 춘계학술대회
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• pp.791-794
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• 2013

본 연구에서는 초기 핵 방사선 조건에서 반도체소자의 과도응답특성을 분석하기 위한 선행연구의 일환으로 반도체 소자의 과도방사선에 의한 영향에 대한 주요원인과 반도체의 물성, 설계구조, 공정방식의 조건에 따라 소자내부에 생성되는 광전류 거동특성에 대한 정략적인 분석을 위한 시뮬레이션 분석을 수행하였으며 결과적으로 반도체소자의 설계조건과 입력되는 과도방사선의 선량율에 따른 비선형 특성을 확인하였다.

• Journal of Semiconductor Engineering
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• 제3권2호
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• pp.161-167
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• 2022

Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• 한국전기전자재료학회논문지
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• 제18권1호
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• pp.17-23
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• 2005

The switching characteristics of MOS-Controlled Thyristor(MCT) is studied with variation of the channel length and impurity concentration in ON and OFF FET channel. The proposed MCT power device has the lateral structure and P-epitaxial layer in substrate. Two dimensional MEDICI simulator and PSPICE simulator are used to study the latch-up current and forward voltage-drop from the characteristics of I-V and the switching characteristics with variation of channel length and impurity concentration in P and N channel. The channel length and N impurity concentration of the proposed MCT power device show the strong affect on the transient characteristics of current and power. The N channel length affects only on the OFF characteristics of power and anode current, while the N doping concentration in P channel affects on the ON and OFF characteristics.

• 대한전자공학회논문지SD
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• 제46권1호
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• pp.1-6
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• 2009

고전압 소자에서 스냅백 이후의 유지 전압은 구동전압에 비해 매우 작아서 고전압 MOSFET이 ESD(ElecroStatic Discharge) 파워클램프로 바로 사용될 경우 래치업 문제를 일으킬 수 있다. 본 연구에서는 스택 바이폴라 소자를 이용하여 래치업 문제가 일어나지 않는 구조를 제안하였다. 제안된 구조에서는 유지 전압이 구동전압 보다 높으므로 래치업 문제가 발생하지 않으면서, 기존의 다이오드를 사용한 고전압 파워클램프에 비해 면적이 작으며, 내구성 측면에서 800% 성능향상이 있게 되었다. 제안된 구조는 $0.35{\mu}m$ 60V BCD(Bipolar-CMOS-DMOS) 공정을 사용하여 제작되었으며, TLP(Transmission Line Pulse) 장비로 웨이퍼-레벨 측정을 하였다.

• 전기학회논문지
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• 제62권5호
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• pp.639-642
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• 2013

In this paper, proposed NED(nuclear event detectors) for detection of a transient radiation. Nuclear event detector was blocked of power temporary for defence of critical damage at a electric device when a induced transient radiation. Conventional NED consist of BJT, resistors and capacitors. The NED supply voltage of 5V and MCM(Multi Chip Module) structures. The proposed NED were designed for low supply voltage using 0.18um CMOS process. The response time of proposed NED was 34.8ns. In addition, pulse radiation experiments using a electron beam accelerator, the output signal has occurred.