• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.34-44
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• 1996

A transputer is a powerful micro-processor, which can communicate with other processors with its own communication links and can be utilized into a powerful parallel computer system with easy way and low price. However, its usage has been limited to a few people because of its own programming language and complicated user interfaces. This paper presents programming tools to use a transputer system easily. It includes transputer integrated environment which has many developing tools, and transputer manager which can monitor and manage the system and developed programs on it. We also implemented a graphichs application program in order to test the feasibility and funcitonalities of programmers easy access to the transputer networks and visualize the performance status of each processor so that they can write efficient parallel programming codes.

• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.397-400
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• 1992

Many dynamic control have been proposed; however, most of them are limited within stage of simulation study. The main reason is that the computations required for inverse dynamics are far beyond the ability of the present commercially available microprocessors. In this paper, In order to achieve real-time processing in robot dynamic control, a parallel processing computer for robot dynamic control is implemented using two transputer. Two transputer compute two degree of freedom robot. The transputer is a special purpose MPU for parallel processing. Transputers are used in networks to build a high performance concurrent system. A network of transputers and peripheral controllers is constructed using point-to-point communication. To gain most benifit from the transputer architecture, the whole system is programmed in OCCAM which is a high level language for concurrent applications. This control algorithm is applied to the RHINO SCARA type manipulator. We could taked about 438.6 microseconds to compute robot dynamic with two-processors.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.647-650
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• 1988

This paper proposes and sketches out a new parallel architecture of transputer-based pyramidal parallel array computer (TPPAC) used to process computationally intensive problems for geometric processing applications such as computer vision, image processing etc. It explores how efficiently the pyramid computer architecture is designed using transputer chips, and poses a new interconnection scheme for TPPAC without using additional transputers.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.7
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• pp.735-741
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• 1992

This paper presents a parallel algorithm for the finite element analysis using relatively inexpensive transputer parallel system. The substructure method, which is highly parallel in nature, is used to improve the parallel computing efficiency by splitting up the whole structure into substructures. The proposed algorithm is applied to a simple two-dimensional magnetostatic problem. It is found that the more the number of transputer is increased, the more the total computation time is reduced. And the computational efficiency becomes better as the number of internal boundary nodes becomes smaller.

• Journal of Biomedical Engineering Research
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• v.17 no.4
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• pp.459-468
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• 1996

This paper considers the problem of realising a parallel EMG identifier used in FES (functional electrical stimulation) system on a fixed dimension transputer array. This involves using an identifiestion algorithm in the wavelet transform domain. This algorithm have suggested by the authors in a previous paper(6). The transputer serial links permit higtlly varied and economic network-type connections and the structure enables rapid topological reconfiguration. Analysing the results Showed that the Speed-UPS ranged from 1.82 to 3.44 With 2-4 transputers for corresponding model order, and from 1.82 to 3.97 with increasing the model orders when two and four transputers are used respectively.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1991.10a
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• pp.6-22
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• 1991

This thesis presents a parallel implementation of an iterative method for large scale, sparse linear system and gives result of computational experiments performed on both single transputer and multi transputer parallel computers. To solve linear system, we use conjugate gradient method and develope data storage techinique, data communication scheme. In addition to the explanation of conjugate gradient method, the result of computational experiment is summarized.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10b
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• pp.446-450
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• 1993

In this paper we propose an arc welding robot system, where two robots works coordinately and employ the vision sensor. In this system one robot arm holds a welding target as a positioning device, and the other robot moves the welding torch. The vision sensor consists of two laser slit-ray projectors and one CCD TV camera, and is mounted on the top of one robot. The vision sensor detects the 3-dimensional shape of the groove on the target work which needs to be weld. And two robots are moved coordinately to trace the grooves with accuracy. In order to realize fast image processing, totally five sets of high-speed parallel processing units (Transputer) are employed. The teaching tasks of the coordinated motions are simplified considerably due to this vision sensor. Experimental results reveal the applicability of our system.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.12 no.2
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• pp.233-241
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• 1999

본 연구는 개별 메모리를 갖는 소결합 구조의 MIMD형 병렬컴퓨터인 트랜스퓨터시스템 하에서 구조최적화를 위한 병렬처리 과정을 보이고 시험모델에 적용하여 타당성 및 효율성을 검증한다. 전체 최적화과정의 대부분을 차지하는 해석 및 민감도 알고리즘은 영역단위의 병렬성을 갖는 부구조화에 근거하고 하드웨어 구성에 맞춰 변환 재구성한다. 각 노드간 통신은 정적응축과 설계도함수에 한정, 그 횟수를 최소화하고 그들을 동기화하므로써 개별메모리형 연산모델의 약점인 통신비용의 문제를 해소한다. PC를 호스트로 한 수치실험은 고속화 효율성 면에서 고무적인 결과를 보여주고 있으며, 이런 점에서 시스템의 확장성을 함께 고려한다면 트랜스퓨터 시스템에 기초한 병렬처리는 공학 환경의 변화와 요구에 부응하는 좋은 대안이 될 수 있다.

• The Journal of the Acoustical Society of Korea
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• v.18 no.5
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• pp.44-51
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• 1999

This paper presents a massively parallel computational model for the efficient integration of speech and natural language understanding. The phoneme model is based on continuous Hidden Markov Model with context dependent phonemes, and the language model is based on a knowledge base approach. To construct the knowledge base, we adopt a hierarchically-structured semantic network and a memory-based parsing technique that employs parallel marker-passing as an inference mechanism. Our parallel speech recognition algorithm is implemented in a multi-Transputer system using distributed-memory MIMD multiprocessors. Experimental results show that the parallel speech recognition system performs better in recognition accuracy than a word network-based speech recognition system. The recognition accuracy is further improved by applying code-phoneme statistics. Besides, speedup experiments demonstrate the possibility of constructing a realtime parallel speech recognition system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.410-424
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• 1993

In this paper, we present new techniques for designing systolic arrya and asynchronous arrays for digital-signal processings. More specifically, we propose a systolic array with simple local interconnections which achieves optimal performance without having undesirable features such as preloading input data or global broadcasting. As asynchronous array for digital-signal processings, which can speed up the total computation time significantly is also which can speed up the total computation time significantly is also presented. The key component of the asynchronous array is a presented. The key component of the asynchronous array is a comunicaiton protocol which controls input data flow properly and efficiently. Finally, performance of the arrays is analyzed and a simulation using Occam programmed in a Transputer network is reported.