• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.132-138
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• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.200-200
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• 2010

이 논문에서는 field-effect mobility를 향상시키기 위해 triple-layer (SiNx/SiO2/SiOxNy stack 구조)를 gate dielectric material 로 LTPS TFTs에 적용하였다. 이는 플라즈마 처리 기법과 적층구조의 효과적인 in-situ 공정을 이용하여 interface trap과 mobile charge를 낮추어 높은 이동도의 결과를 생각하고 실험하였다. 실험은 SiO2 gatedielectric과 triple-gate dielectric의 C-V curve를 1 MHz의 주파수에서 측정하였다. 또한 Transfer characteristics를 single SiO2 gatedielectric과 triple-gate dielectric of SiNx/SiO2/SiOxNy를 STA 장비를 이용해 측정하였다. 위의 측정을 통해 threshold voltage, mobility, subtheshold swing, driving current, ON/OFF current ratio를 비교 분석하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.92-92
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• 2009

본 논문에서는 strained Silicon-on-Insulator (sSOI) 기판에 제작된 triple-gate MOSFETs 의 이동도와 단채널 효과에 대하여 분석 하였다. Strained 실리콘에 제작된 소자는 전류의 방향이 <110> 밤항일 경우 전자의 이동도는 증가하나 정공의 이동도는 오히려 감소하는 문제점이 있다. 이를 극복하기 위하여 소자에서 전류의 방향이 <110>방향에서 45 도 회전된 <100> 방향으로 흐르게 제작하였다. Strain이 가해지지 않은 기판에 제작된 동일한 구조의 소자와 비교하여 sSOI 에 제작된 소자에서 전자의 이동도는 약 40% 정공의 이동도는 약 50% 증가하였다. 채널 길이가 100 nm 내외로 감소함에 따라 나타나는 drain induced barrier lowering (DIBL) 현상, subthreshold slope (SS)의 증가 현상에서 sSOI에 제작된 소자가 상대적으로 우수한 특성을 보였으며 off-current leakage ($I_{off}$) 특성도 sSOI기판이 더 우수한 특성을 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.271-276
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• 2017

The triple-gate tunnel FETs encapsulated with an epitaxial layer (EL TFETs) is proposed to lower the subthreshold swing of the TFETs. Furthermore, the band-to-band tunneling based on the maximum electric-field can occur thanks to the epitaxial layer wrapping the Si fin. The performance and mechanism of the EL TFETs are compared with the previously proposed TFET based on simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.302-310
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• 2008

This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.1-7
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• 2012

We have developed a new gate driver circuit for liquid crystal displays using oxide thin-film transistors (TFTs). In the new gate driver, negative gate bias is applied to turn off the oxide TFTs because the oxide TFT occasionally has negative threshold voltage (VT). In addition, we employed three parallel pull-down TFTs that are turned on in turns to enhance the stability. SPICE simulation showed that the proposed circuit worked successfully covering the VT range of -3 V ~ +6 V And fabrication results confirmed stable operation of the new circuit using oxide TFTs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.