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VLSI Design of Cryptographic Processor for SEED and Triple DES Encryption Algorithm (SEED 와 TDES 암호 알고리즘을 구현하는 암호 프로세서의 VLSI 설계)

  • 정진욱;최병윤
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.169-172
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    • 2000
  • This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

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VLSI Design of Cryptographic Processor for Triple DES and DES Encryption Algorithm (3중 DES와 DES 암호 알고리즘용 암호 프로세서와 VLSI 설계)

  • 정진욱;최병윤
    • Proceedings of the Korea Multimedia Society Conference
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    • 2000.04a
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    • pp.117-120
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    • 2000
  • This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

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Applicability of Color Corescanner to the Analysis and Data-base of Drill Cores (시추코어 분석 및 데이터베이스화를 위한 칼라 코어스캐너의 응용)

  • ;Ghodrat Rafat
    • Proceedings of the Korean Geotechical Society Conference
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    • 2001.03a
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    • pp.249-256
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    • 2001
  • Optical Color Corescanner firstly developed by DMT-GeoTec, Germany and further upgraded through the Korea-Germany joint project is capable of duplicating the core surfaces. The tool uses a digital CCD line camera. As the core is rotated by an electric motor, the camera scans the uppermost line, everytime with a circumferential increment of up to 0.05mm(20pixels/mm) and hence a complete 360$^{\circ}$ unwrapped image(core image) is produced. This paper illustrated diverse research benefits of such core images from several test sites in our country. All scanned images could be stored as a data-base one and easily used with software facilities \circled1 to evaluate a percental distribution of mineral components or grain size etc. not only for the rock classification but also for e.g. the assessment of building stones, \circled2 to study potential reservoirs as a hydrocarbon indicator using ultraviolet fluorescence reflection from cores, \circled3 to facilitate the qualitative and quantitative analysis of fractures, \circled4 to evaluate the fractures and thin bedded reservoirs using spectral color responses. Based on abundant scanning experiments, it would seem that this imaging work should lead to reflecting the future trend in underground survey toward a more comprehensive understanding of the properties and behaviors of in situ rocks.

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