• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.242-242
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• 2009

Fabrication of Anodic aluminum oxide under DC vias condition has been studied. When bias and time of anodic aluminum oxide process change, the hole distance and diameter size change. Comparison of fabricated AAO between AC vias and DC vias condition has been studied in this experiment. The first and second anodization of one aluminum is done by using DC and AC power supplier. And first and second anodization of another aluminum is done by DC power supplier. The size of the aluminum is $1cm{\times}3cm$, and second anodic aluminum oxide process takes about 45min. It is found that the hexagonal shape appears on the surface of the AAO. AC power source can fabricate aao which have a nano hole array. We can see that the hole on the surface of the AC vias has a better rounded hole than DC vias AAO. we need more data so we can get characteristic about AC power generated AAO.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.5
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• pp.351-355
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• 2001

Via for achieving reliable fabrication of MCM(Multichip Module) substrate was formed on photosensitive BCB layer. The MCM substrate consists of photosensitive BCB(Benzocyclobutene) interlayer dielectric and copper conductors. In order to form the vias in the photosensitive BCB layer, the process of forming the BCB layer and its via forming plasma etch using C$_2$F$\_$6//O$_2$ gas were evaluated. The thickness of the BCB layer after hard bake was shrunk down to 40% of the original. The resolution of vias formed on the BCB was 15㎛ and the slope after develop was 85 degree. AES analysis was done on two vias, one is etched in C$_2$F$\_$6/O$_2$ gas and the other isnot etched. On the via etched in C$_2$F$\_$6//O$_2$, native C was detected and the amount of native C was reduced after Ar sputter. On the via not etched in C$_2$F$\_$6//O$_2$, organic C was detected. As a result of AES, BCB residue was not removed by Ar sputter, so plasma etch is necessary for achieving reliable vias.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.6 s.109
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• pp.529-537
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• 2006

Multi-layer PCBs are of ien used In compact microwave circuit design as density of PCB layout is increased. In this paper, the crosstalk between coupled lines connected with vias in a 4-layer PCB is investigated theoretically based on the circiuit-concept approach. Coupled lines connected with vias in a 4-layer PCB are divided into three sections, which are coupled microstrip lines and upper via section, center via section, and lower via and coupled microstrip lines section, respectively. Each section is represented by ABCD matrix. By cascading these three ABCD matrices crosstalk between coupled lines connected with vias in a 4-layer PCB is approximately calculated. The validity of this theoretical approach is verified by comparing the calculated results with the simulated ones using HFSS.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.63-69
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• 2007

We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.213-220
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• 2006

This paper investigates how the PCB power-bus sturcture's characteristics are influenced by the loading of decoupling capacitors in conjunction to other lumped elements including vias. The fields and impedance profiles are rigously evaluated and analyzed on various cases loaded with the above components and their effects will be given to bring better PCB EMC countermeasurs.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.429-432
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• 2005

This paper investigates how the PCB power-bus structure's characteristics are influenced by the loading of decoupling capacitors that are placed close to vias, on purpose or not. It is worthwhile to see the correlated effects of the aforementioned lumped elements in that when they inevitably share one DC power-bus they will result in positive or negative changes in the PCB EMC design. The EM fields and impedance profiles are rigously calculated on the PCB power-bus cases loaded with the above components and their effects will be given to bring better PCB EMC countermeasures.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.53-57
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• 2014

Thin glass (< 100 microns) is a promising material from which advanced interposers for high density electrical interconnects for 2.5D chip packaging can be produced. But thin glass is extremely brittle, so mechanical micromachining to create through glass vias (TGVs) is particularly challenging. In this article we show how laser processing using deep UV excimer lasers at a wavelength of 193 nm provides a viable solution capable of drilling dense patterns of TGVs with high hole counts. Based on mask illumination, this method supports parallel drilling of up over 1,000 through vias in 30 to $100{\mu}m$ thin glass sheets. (We also briefly discuss that ultrafast lasers are an excellent alternative for laser drilling of TGVs at lower pattern densities.) We present data showing that this process can deliver the requisite hole quality and can readily achieve future-proof TGV diameters as small $10{\mu}m$ together with a corresponding reduction in pitch size.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.49-53
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• 2009

In order to investigate the formation behavior of hollow Cu via for MEMS packaging, we observed the microstructure of the Cu vias and measured the average thickness and the thickness deviation with variations of pulse-reverse pulse current density and electrodeposition time. With electrodeposition for 3 hours at the pulse and reverse pulse current densities of $-5\;mA/cm^2$ and $15\;mA/cm^2$, the average thickness and the thickness deviation of the Cu vias were $5\;{\mu}m$ and $0.63\;{\mu}m$, respectively. With increasing the electrodeposition time to 6 hours, it was possible to form the Cu vias, of which the average thickness and thickness variation of the Cu vias were $10\;{\mu}m$ and $1\;{\mu}m$, respectively. With increasing the pulse and reverse pulse current densities to $-10\;mA/cm^2$ and $30\;mA/cm^2$, Cu vias of uniform thickness could not be formed due to the faster increase of the thickness deviation than that of the average thickness with increasing the electrodeposition time.

• Journal of the korean veterinary medical association
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• v.30 no.5
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• pp.299-302
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• 1994