• Title/Summary/Keyword: voltage multiplier

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Design of Voltage Multiplier based on Charge Pump using Modified Voltage Doubler Circuit (배전압 회로를 적용한 변형된 Charge Pump 기반 전압 증배기 설계)

  • Yeo, Hyeop-Goo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.8
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    • pp.1741-1746
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    • 2012
  • This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generates about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

RF-DC Voltage Multiplier Design and Fabrication for 5.8GHz Microwave Wireless Power Transmission (5.8GHz 마이크로파 무선전력전송을 위한 RF-DC 전압 체배기 설계 및 구현)

  • Lee, Seong Hun;Son, Myung Sik
    • Journal of the Semiconductor & Display Technology
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    • v.16 no.2
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    • pp.85-88
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    • 2017
  • In this paper, we have designed and fabricated a RF-DC voltage multiplier for 5.8GHz microwave wireless power transmission. In order to obtain higher voltage, the RF-DC voltage multiplier with 10 diodes (D-10) and the receiver module with an antenna and BPF (Band Pass Filter) was manufactured. The measured and compared results show that the voltages of the proposed one are lower than those of the previous tripler module up to 40cm. However, the voltage of the proposed one with the voltage multiplier is higher than that of the tripler module at the distances of 45cm and 50cm due to the voltage multiplier with 10 diodes.

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The Low Voltage Analog Multiplier Using The Bulk-driven MOSFET Techniques (Bulk-Driven 기법을 이용한 저전압 Analog Multiplier)

  • 문태환;권오준;곽계달
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.301-304
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    • 2001
  • The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

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Simulation Results of the 4 stage Single Flux Quantum Voltage Multiplier (4 stage 단자속 양자 Voltage Multiplier의 Simulation 결과)

  • Chu, Hyung-Gon;Jung, Ku-Rak;Kang, Joon-Hee
    • 한국초전도학회:학술대회논문집
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    • v.9
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    • pp.238-241
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    • 1999
  • Analog-to-digital converter has attracted a lot of interests as one of the most prospective area of an application of Josephson Junction technology. Recently, the development of a digital-to-analog converter has been pursued to achieved the high performance. One of the main advantage in using single flux quantum logic in a digital-to-analog converter is the low voltage drop in a single Josephson Junction and hence the resolution of the output voltage of this digital-to-analog converter can be very high. In this work, we have used a software, called WRspice, to study a voltage multiplier circuit which is the basic block in building a digital-to-analog circuit. In simulation, we operated a voltage multiplier with .4 Josephson Junctions per stage and studied the dependence on the circuit bias currents and the circuit inductors of the voltage multiplier. Our simulation results showed a fast operation and reasonable circuit margins.

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Design of Low voltage CMOS Analog Four-Quadrant Multiplier (저전압 CMOS 아날로그 4상한 멀티플라이어 설계)

  • 유영규;박종현;윤창훈;김동용
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.244-247
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    • 1999
  • In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of a pair of transconductor and lowers supply voltage down to $V_{T}$+2 $V_{Ds,sat}$+ $V_{DS,triode}$. The designed analog four-quadrant multiplier have simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7 $V_{p-p}$././.

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Design Consideration of the Voltage Multiplier of UHF RFID Tag for Increased Reading Range (인식거리 향상을 위한 UHF 대역 RFID 태그용 전압체배기 설계)

  • Lee, Jong-Wook;Lee, Bom-Son
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.587-590
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    • 2005
  • We investigated the input impedance characteristics of UHF-band RFID tag chip for increased reading range. A voltage multiplier designed using 0.4 ${\mu}m$ $zero-V_T$ MOSFET showed that DC output voltage of 2 V can be obtained using standard CMOS process. The input impedance of the voltage multiplier was examined to achieve impedance level for maximum reading distance using analytical and numerical approaches. The input impedance of the voltage multiplier could be varied in a wide range by selecting the size of MOSFET and the number of multiplying stages of the voltage multiplier, and thus, the impedance level required for the tag antenna can be obtained in presence of other tag circuit blocks.

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Design of a Voltage Multipler Circuit using a Modified Voltage Doubler (개선된 배전압 회로를 이용한 전압증배기 회로 설계)

  • Yeo, Hyeop-Goo;Jung, Seung-Min;Sonh, Seung-Il;Kang, Min-Koo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.696-698
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    • 2012
  • This paper introduces a new DC-DC voltage multiplier using a Dickson's charge pump and a modified voltage doubler. The voltage obtained from a conventional Dickson's chrage pump was reused for accelerating the voltage multiplication and the architecture of the proposed voltage multiplier would not decrease the device reliability of DMOS. The proposed 6-stage voltage multiplier generate about 33V with 3V voltage source. To evaluate the proposed voltage multiplier, simulations were performed with Magna DMOS technology. The simulated voltage multiplication agrees well with a theoretical value, therefore, this paper introduces a new fast voltage multiplier with minimum devices.

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An Analysis of Voltage Multiplier Circuits for Smart Phone RF Wireless Charging (스마트폰 RF 무선충전을 위한 전압 체배기 회로 분석)

  • Son, Myung Sik
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.2
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    • pp.29-33
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    • 2021
  • A 5.8-GHz 1W wireless power transmission system was used for charging a smart phone. The voltage of one RF power receiver with antenna was not enough for charging. Several power receivers for charging a smart phone was connected serially. The voltage of several RF power receivers are highly enough for charging a smart phone within 50cm. However, the lack of current from small capacitances of RF-DC converters is not suitable for charging smart phone. It means very long charging time. In this paper, the voltage multiplier circuits for RF-DC converters were analyzed to increase the current and voltage at the same time to reduce the charging time in smartphone RF wireless charging. Through the analysis of multiplier circuits, the 7-stage parallel multiplier circuit with voltage-doubler units are suitable for charging the smartphone, which supplies 5V and 700mA at 3V@5.8GHz.

Design of a 64×64-Bit Modified Booth Multiplier Using Current-Mode CMOS Quarternary Logic Circuits (전류모드 CMOS 4치 논리회로를 이용한 64×64-비트 변형된 Booth 곱셈기 설계)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.14A no.4
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    • pp.203-208
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    • 2007
  • This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

Voltage-Mode CMOS Squarer/Multiplier Circuit

  • Bonchu, B.;Surakampontorn, W.
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.646-649
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    • 2002
  • In this paper, a low-voltage CMOS squarer and a four-quadrant analog multiplier are presented. It is based on a source-coupled pair and a scaled-floating voltage generator which are modified to work as a voltage squaring and a sum/difference circuits. The proposed squarer/multiplier have been simulated with HSPICE, where -3㏈ bandwidth of 10MHz is achieved. The power consumption is about 0.6㎽, from a ${\pm}$1.5V supply, and the total harmonic distortion is less than 0.7%, with a 1.2V peak-to-peak 1MHz input signal.

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