• Title/Summary/Keyword: wafer level package

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Wafer Level Package Using Glass Cap and Wafer with Groove-Shaped Via (유리 기판과 패인 홈 모양의 홀을 갖는 웨이퍼를 이용한 웨이퍼 레벨 패키지)

  • Lee, Joo-Ho;Park, Hae-Seok;Shin, Jea-Sik;Kwon, Jong-Oh;Shin, Kwang-Jae;Song, In-Sang;Lee, Sang-Hun
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.12
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    • pp.2217-2220
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    • 2007

  • In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.

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Large Area Wafer-Level High-Power Electronic Package Using Temporary Bonding and Debonding with Double-Sided Thermal Release Tape (양면 열박리 테이프 기반 임시 접합 공정을 이용한 대면적 웨이퍼 레벨 고출력 전자패키지)

  • Hwang, Yong-Sik;Kang, Il-Suk;Lee, Ga-Won
    • Journal of Sensor Science and Technology
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    • v.31 no.1
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    • pp.36-40
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    • 2022

  • High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

  • https://doi.org/10.46670/JSST.2022.31.1.36 인용 PDF KSCI

High-density Through-Hole Interconnection in a Silicon Substrate

  • Sadakata, Nobuyuki
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2003.09a
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    • pp.165-172
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    • 2003

  • Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

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Antifuse Circuits and Their Applicatoins to Post-Package of DRAMs

  • Wee, Jae-Kyung;Kook, Jeong-Hoon;Kim, Se-Jun;Hong, Sang-Hoon;Ahn, Jin-Hong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.4
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    • pp.216-231
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    • 2001

  • Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

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A Novel Chip Scale Package Structure for High-Speed systems (고속시스템을 위한 새로운 단일칩 패키지 구조)

  • 권기영;김진호;김성중;권오경
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.11a
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    • pp.119-123
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    • 2001

  • In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.

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