• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.118-129
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• 2010

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

• 한국산업정보학회논문지
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• 제18권5호
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• pp.19-23
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• 2013

본 논문에서는 고속 데이터 처리용 TCAM(Ternary Content Addressable Memory) 설계를 위하여 6T SRAM cell의 안정성 분석 방법에 대해 기술하였다. TCAM은 고속 데이터 처리를 목적으로 하기 때문에 동작 주파수가 높아질수록 필요 시 되는 CMOS 공정의 단위가 작아지게 된다. 공급 전압의 감소는 TCAM 동작에 불안정한 영향을 줄 수 있으므로 SRAM cell 안정성 분석을 통한 TCAM 설계가 필수적이다. 우리는 6T SRAM의 정적 노이즈 마진(SNM)을 측정하여 분석하였고, TCAM의 모든 시뮬레이션은 $0.18{\mu}m$ CMOS 공정을 사용하여 확인하였다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2006년도 ISMP 2006
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• pp.293-316
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• 2006

[ $\blacksquare$ ] I/O Signal $\square$ We see adequate margin for the RC B design $\square$ Minimum ODW value is 328ps using Ac to DC measurement for the read case. $\square$ Minimum ODW value is 350ps using AC to DC mesurement method for the write case. $\blacksquare$ CLK Signal $\square$ The slew-rate decreases when the Cterm value increases $\square$ Lower slew-rate could effect delay and jitter. $\square$ There are some ldge issues during transitions with lower Cterm and without Cterm. $\square$ Our recommendation for the Cterm value range is between 1.5pF to 2.4pF. $\blacksquare$ ADD/CMD/Ctrl Signal $\square$ High output slew-rate at low VDD causes ring back that reduces voltage margin because of x-talk. $\square$ 30ohm Rterm for the CTRL signal shows a better signal integrity result compared to 36ohm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.647-650
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• 2005

In this paper, a low voltage SRAM using double boosting scheme is described. A low supply voltage deteriorates the static noise margin (SNM) and the cell read-out current. For read/write operation, a selected word line and cell VDD bias are boosted in a different level using double boosting scheme. This increases not only the static noise margin but also the cell readout current at a low supply voltage. A low voltage SRAM with 32K ${\times}$ 8bit implemented in a 0.18um CMOS technology shows an access time of 26.1ns at 0.8V supply voltage.

• ETRI Journal
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• 제29권4호
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• pp.457-462
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• 2007

This work presents a low-voltage static random access memory (SRAM) technique based on a dual-boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read-out current. A 0.18 ${\mu}m$ CMOS 256-kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 ${\mu}W$/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.37-50
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• 2009

Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random $V_T$ variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing $V_T$ variation (${\sigma}_{VT}$). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if ${\sigma}_{VT}$ can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권8호
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• pp.407-414
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• 2004

In this paper, a new gray scale expression method that divides the scan lines into multiple blocks is suggested. The proposed method can drive 16 sub-fields per 1 TV field in the panel with XGA ($1366{\times}768$) resolution. The on and off states of even subfields depend on the condition of odd subfields. The write address mode is used in the odd subfields, while the erase address mode is used in the even subfields. Because the ramp reset pulse is applied every 2 sub-fields, both the contrast ratio and the dynamic voltage margin are sufficiently obtained in comparison with previous AWD (Address While Display) methods. In realizing 16 subfields, shortening the scan time in the erase address period was important. The X bias voltage in the erase address period affected the minimum address voltage but did not the delay time of the address discharge. The delay time of the address discharge was affected by the address voltage and the time interval between the last sustain discharge and the scanning time. We also evaluated the dynamic false contour. New method shows an improved image quality in horizontal moving, but discontinuous lines were observed at the boundaries of each block in vertical moving

• 정보과학회 논문지
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• 제41권11호
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• pp.878-884
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• 2014

파일 시스템 버퍼 캐시는 느린 스토리지의 접근 횟수를 줄여 입출력 성능 향상에 기여하지만, 캐시에서 수정된 데이터를 스토리지에 오랫동안 반영하지 않을 경우 크래쉬 발생 시 최신 데이터가 유실되거나 데이터의 일관성이 깨어지는 문제가 발생할 수 있다. 이를 방지하기 위해 대부분의 운영체제는 수정 데이터를 주기적으로 스토리지에 반영하는 flush 데몬을 사용한다. 본 논문은 파일시스템의 쓰기 연산 중 30-70%가 주기적인 flush에 의해 발생함을 분석하고, 이를 소량의 NVRAM 버퍼 캐시를 이용하여 해결하는 기법을 제시한다. 특히, 본 논문은 델타 쓰기 및 그룹 기반 교체 기법을 제안하여 소량의 NVRAM 만으로 스토리지 쓰기 트래픽과 처리량을 각각 44.3%와 23.6% 개선할 수 있음을 보인다.

• 대한전자공학회논문지SD
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• 제44권1호
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• pp.28-35
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• 2007

SRAM의 전체적인 성능은 공급 전원전압에 크게 영향을 받는다. 본 논문에서는 1-V 이하의 저전압 동작시 주요 이슈가 되는 SRAM 셀의 SNM(Static Noise Margin)과 셀 전류의 크기를 개선하기 위하여 이중 승압 셀 바이어스 기법을 이용한 SRAM 설계기법에 대해 기술하였다. 제안한 설계기법은 읽기 및 쓰기동작시 선택된 SRAM 셀의 워드라인과 load PMOS 트랜지스터의 소스에 연결된 셀 공급전원을 서로 다른 레벨로 동시에 승압함으로써 SRAM 셀의 SNM과 셀 전류를 증가시킨다. 이는 셀 면적의 증가 없이 충분한 SNM을 확보할 수 있으며, 아울러 증가된 셀 전류에 의해 동작속도가 개선되는 장점이 있다. $0.18-{\mu}m$ CMOS 공정을 적용한 0.8-V, 32K-byte SRAM macro 설계를 통해 제안한 설계기법을 검증하였고, 시뮬레이션 결과 0.8-V 공급전원에서 종래의 셀 바이어스 기법 대비 135 %의 SNM 향상과 아울러 동작속도는 31 % 개선되었으며, 이로인한 32K-byte SRAM은 23 ns의 access time, $125\;{\mu}W/Hz$의 전력소모 특성을 보였다.