A new IGBT structure for suppression of latch up with selective N+ buffer layer

Selective N+ 버퍼층을 갖는 latch up 억제를 위한 새로운 IGBT 구조

A novel structure, which can suppress latch-up phenomena, is proposed and verified by the PISCESIIB simulation. It is shown that this structure employing the selective N+ buffer layer increases latch-up current density due to suppression of the current flowing through the p-body. The width of the N+ buffer layer is optimized considering the trade-off between the latch-up current density and the forward voltage drop. The selective buffer layer results in an improved trade-off relationship compared with the uniform buffer layer.