대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Raptor의 정수처리기 설계

Design of the Integer Processor Unit for RAPTOR

  • 송윤섭 (고려대학교 전자공학과 ASIC 연구실) ;
  • 김도형 (고려대학교 전자공학과 ASIC 연구실 고려대학교 정보공학과 병렬연산연구실 한국전자통신연구원 컴퓨터시스템연구부)
  • 발행 : 1998.10.01
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초록

This paper describes the microarchitecture of the integer processor unit of RAPTOR which is an on-chip multiprocessor. The integer processor unit implements the 64-bit SPARC-V9 architecture and supports by hardware out-of-order instruction execution. The unit is designed to be handy so that multiple copies of the unit cn be integrated with cache memories into a single chip. The design was proceeded in a top-down manner. The hardware description and its verfication were performed using Verilog-HDL.

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