RAPTOR의 명령어 페치 유닛 설계

Design of an Instruction Fetch Unit for RAPTOR, a On-Chip Multiprocessor

  • 이성권 (고려대학교 정보공학과 병렬연산연구실) ;
  • 오형철이상원한우종 (고려대학교 정보공학과 병렬연산연구실 고려대학교 전자공학과 ASIC 연구실 한국전자통신연구원 컴퓨터시스템연구부)
  • 발행 : 1998.10.01

초록

This paper introduces an instruction fetch unit which is designed for RAPTOR, an on-chip multiprocessor. In order to reduce control hazards, the proposed fetch unit supports a hybrid branch prediction scheme which consists of a static scheme and the 2bC branch prediction scheme. The fetch unit also utilizes the branch folding technique with two instruction buffers to avoid the branch penalty caused by imspredictions. Instructions are predecoded in the fetch unit to achieve extra performance gain.

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