PLL 고정시간의 저감대책 수립과 저 지터 구현을 위한 위상-주파수 감지기의 설계

A Design of Phase-Frequency Detector for Low Jitter and Fast Locking Time of PLL

In this paper, a new precharge type PFD for fast locking time of PLL is suggested. It is realized by inserting NMOS transistor and inverter into the precharge part of PFD for isolating the reset of the Up signal from the feedback signal. The new precharge type PFD generates the Up signal while the feedback signal is fixed at a high level. Therefore the new PFD output is increased than the conventional precharge type PFD output. As a result of the increased PFD output, fast locking of PLLs is achieved. Additionally, with control the falling time of the inverter, the dead-zone is reduced and the jitter characteristics are improved. The whole characteristics of PFD and PLL are simulated by using HSPICE. Simulation results show that the dead-zone is 20ps and the locking time of PLL using the new PFD is 38ns at the 350MHz frequency of referecne signal. This value is quite small compared with conventional PFD.