대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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A Test Input Sequence for Test Time Reduction of $I_{DDQ}$ Testing

  • Ohnishi, Takahiro (Department of Electrical and Electronic Engineering Faculty of Engineering, The Univ. of Tokushima) ;
  • Yotsuyanagi, Hiroyuki (Department of Electrical and Electronic Engineering Faculty of Engineering, The Univ. of Tokushima) ;
  • Hashizume, Masaki (Department of Electrical and Electronic Engineering Faculty of Engineering, The Univ. of Tokushima) ;
  • Tamesada, Takeomi (Department of Electrical and Electronic Engineering Faculty of Engineering, The Univ. of Tokushima)
  • 발행 : 2000.07.01
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초록

It is shown that $I_{DDQ}$ testing is very useful for shipping fault-free CMOS ICs. However, test time of $I_{DDQ}$ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of $I_{DDQ}$ testing. At first, it is Shown that $I_{DDQ}$ test time Will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed. The feasibility is checked by some experiments.riments.

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