Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
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A STUDY ON THE ELECTRICAL CHARACTERISTICS OF ORGANIC THIN FILM TRANSISTORS WITH SURFACE-TREATED GATE DIELECTRIC LAYER

표면 처리한 $SiO_2$를 게이트 절연막으로 하는 박막 트랜지스터의 특성 연구

  • Lee, Jae-Hyuk (Dept. of Electrical and control Eng., Hongik Univ.) ;
  • Lee, Yong-Soo (Dept. of Electrical and control Eng., Hongik Univ.) ;
  • Park, Jae-Hoon (Dept. of Electrical and control Eng., Hongik Univ.) ;
  • Choi, Jong-Sun (Dept. of Electrical and control Eng., Hongik Univ.) ;
  • Kim, Eu-Gene (Dept. of Basic science, Hongik Univ.)
  • 이재혁 (홍익학교 전기제어공학과) ;
  • 이용수 (홍익학교 전기제어공학과) ;
  • 박재훈 (홍익학교 전기제어공학과) ;
  • 최종선 (홍익학교 전기제어공학과) ;
  • 김유진 (홍익대학교 기초과학과)
  • Published : 2000.11.25
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Abstract

In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces, where the gate dielectrics were treated by the two methods which are the deposition of Octadecyltrichlorosilane (OTS) on the insulator and rubbing the insulator surface. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-7}$ Torr and at a deposition rate of $0.3{\AA}/sec$. Aluminum and gold were used for the gate and source/drain electrodes. OTS is used as a self-alignment layer between $SiO_2$ and pentacene. The gate dielectric surface was rubbed before pentacene is deposited on the insulator. In order to confirm the changes of the surface morphology the atomic force microscopy (AFM) was utilized. The characteristics of the fabricated TFTs are measured to clarify the effects of the surface treatment.

Keywords