Digital Gray-Scale/Color Image-Segmentation Architecture for Cell-Network-Based Real-Time Applications

This paper proposes a digital algorithm for gray-scale/color image segmentation of real-time video signals and a cell-network-based implementation architecture in state-of-the-art CMOS technology. Through extrapolation of design and simulation results we predict that about 300$\times$300 pixels can be integrated on a chip at 100nm CMOS technology, realizing very high-speed segmentation at about 1600sec per color image. Consequently real-time color-video segmentation will become possible in near future.